Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

Sun, Hongbin; Liu, Jibang; Anigundi, Rakesh; Zheng, Nanning; Lu, James; Rose, K.; Zhang, Tong

doi:10.1109/mdt.2009.93

Cited by 14 publications

(5 citation statements)

References 14 publications

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“…By folding the DRAM bank layers into 4 layers and then share the same TSVs bus to the logic layers, it reduces the energy from transferring entire row signals. Another work on heterogeneous stacking is done by [12], where they stacked heterogeneous DRAM layers on processor layers. Performance analysis is done using software simulation based on modified CACTI and M5 simulators for full system simulation with multicore processor.…”

Section: Related Workmentioning

confidence: 99%

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Jabbar

M'zah

Hammami

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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The need for higher performance devices to enable more complex applications continues to drive the growth of electronic design especially in the mobile markets. 3D integration is one of the feasible technologies to increase the system's performance and device integration by stacking multiple dies interconnected using through silicon vias (TSV). NoC-based Multiprocessor System on Chip (MPSoC) architecture has become the primary technology to provide higher performance to support more complex applications. In this paper, we perform an exploration and analysis of 2D EDA tool parameters impact on the 3D MPSoC architectures (3D Mesh MPSoC and heterogeneous 3D MPSoC stacking) performance in terms of timing and power characteristics. Exploration results show that the 2D EDA tool parameters have strong impact on the timing performance compared with power consumption. Furthermore, it is also shown that heterogeneous 3D MPSoC architecture has less footprint area, higher speed and less power consumption compared with 3D Mesh MPSoC for the same number of processing elements suggesting that it is a better design approach considering the limitation capability of 2D EDA tools for 3D design.

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Section: Related Workmentioning

confidence: 99%

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Jabbar

M'zah

Hammami

et al. 2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

View full text Add to dashboard Cite

show abstract

“…By folding the DRAM bank layers into four layers and then share the same TSVs bus to the logic layers, it reduces the energy from transferring entire row signals. Another work on heterogeneous stacking is done by [3] where they stacked heterogeneous DRAM layers on processor layers. Performance analysis is done using software simulation based on modified CACTI and M5 simulators for full system simulation with multicore processor.…”

Section: Related Workmentioning

confidence: 99%

Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation

Jabbar

Houzet

Hammami

2013

Fifth Asia Symposium on Quality Electronic Design (ASQED 2013)

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3D integration is one of the feasible technologies for producing advanced computing architecture to support everincreasing demand of higher performance computing especially in mobile devices. The emerging trend of multiprocessor architecture has made Network on Chip (NoC) architecture the best solution for future manycore architecture devices. In this work, we explore the implementation of heterogeneous 3D Multiprocessor System on Chip (MPSoC) stacking architecture and evaluate its performance in terms of timing and power consumption compared with its 2D counterpart. The proposed heterogeneous 3D MPSoC implementation approach is considered to be the best solution for the time being as there are no 3D-aware EDA tools available in the markets that capable of performing 3D optimization as in 2D EDA tools. We also perform physical implementation analysis on the clock tree structure between 2D and 3D architecture and examine the impact of using 2D EDA tools for designing 3D architecture. The implementation is based on industryspecific Tezzaron 3D IC technology and the evaluation is based on the GDSII results from physical design implementations.

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“…This is advantageous for applications, in which components with different requirements are integrated to a single SoC: [9] introduces an architecture for Internet of Things (IoT) stacking wireless sensors, RF communication, data processing and energy scavenging. In highperformance processors, interleaving of dedicated dies with either memory or processing increases performance [10], with exemplary designs [11]- [14]. Especially, vision applications can profit of heterogeneity: 3D VSoCs [4] combining image sensing, mixed-signal conversion and digital image processing.…”

Section: Introductionmentioning

confidence: 99%

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures

et al. 2019

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Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip. A special characteristic of communication networks in heterogeneous 3D SoCs is the varying latency and throughput in each layer. As shown in this work, this variance drastically degrades the network performance. We contribute a co-design of routing algorithms and router microarchitecture that allows to overcome these performance limitations. We analyze the challenges of heterogeneity: Technology-aware models are proposed for communication and thereby identify layers in which packets are transmitted slower. The communication models are precise for latency and throughput under zero load. The technology model has an area error and a timing error of less than 7.4% for various commercial technologies from 90 to 28nm. Second, we demonstrate how to overcome limitations of heterogeneity by proposing two novel routing algorithms called Z + (XY)Z − and ZXYZ that enhance latency by up to 6.5× compared to conventional dimension order routing. Furthermore, we propose a high verticalthroughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers. We achieve an increased throughput of 2 to 4× compared to a conventional router. Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieve improved flit latency of up to 2.26× at small total router area costs between 2.1% and 10.4% for realistic technologies and application scenarios. INDEX TERMS 3D integrated circuits, network on chip, heterogeneous integration, monolithic stacking.

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Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

Cited by 14 publications

References 14 publications

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Exploration of 2D EDA tool impact on the 3D MPSoC architectures performance

Heterogeneous stacking of 3D MPSoC architecture: Physical implementation analysis and performance evaluation

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures

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