Design of 3T Gain Cell for Ultra Low Power Applications

Abstract

Design of a power efficient SRAM cell is one of the most important factor in order to achieve better chip performance. This paper presents a stable SRAM Gain Cell for low power applications. The 6T SRAM has been the traditional choice for the implementation of embedded memories due to its high-access speed and refresh-free static data retention. However, the 6T bit cell has several drawbacks in modern systems, which includes its large transistor count. In order to provide full CMOS logic compatibility a gain-cell (GC)-embedded DRAM (eDRAM) consisting of 3-transistor (3T), GC-eDRAMs which provides a reduced silicon footprint, along with inherent two-port functionality, nonratioed circuit operation, and very low static leakage currents from VDD to GND. With the benefit of read and write access, we modify the 8-TSRAM cell as 3-T SRAM cell with transmission gate that reduces the read and write time access with comparatively low power and eliminating the usage of signal booster. In this paper we designed the 3T GC cell by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology. Key Words: Low power, Gain cell (GC), 3T (3 Transistor), SRAM, I.INTRODUCTION Today world aims in designing low power devices due to the rampant usage of portable battery powered gadgets. Scaling of MOS technology creates new challenges to the SRAM circuit design, mainly leakage power and stability. SRAM design furnishes an approach towards reduces the hold power dissipation devices due to the uncontrolled usage of portable battery powered gadgets. . The proposed cell has similar structure to conventional 6T SRAM cell with the addition of two buffer transistors, one tail transistor and one complementary word line. Dueto stacking effect, the proposed cell achieves lower power dissipation. In this paper, impact of process parameters variations on various design metrics of the proposed cell are presented and compared with conventional differential 6T (D6T),transmission gate based 8T (TG8T) and single ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage and length, on different design metrics of an SRAM cell like, read static noise margin (RSNM), read access time(TRA) and write access time (TWA) are also presented. In deep submicron technology, system-on-chip (SoC) products requires a high speed memory to support increased storage capability. Furthermore static random access memory (SRAM) is widely used for SoC products. Static Random Access Memories (SRAMS) would utilized Likewise cache memory which need aid inserted to microprocessor, System-on-Chip (SoC), Network-on-Chip (NoC) modules. This will be because of those certainty that they would quick contrasted with eDRAM (such Likewise DRAM) Furthermore primary memory (DRAM) [1].They need to be created on the same die of a processor. Concerning illustrations expressed by ITRS, 90% of the processor's chip region is possessed by SRAM [2].increase in processor's speed has risen in recent years, whereas memory speed ...