Design of 7 GHz Microstrip Patch Antenna for Satellite IoT- and IoE-Based Devices

Sharma, Manvinder; Sharma, Bikramjit; Gupta, Anuj; Singla, Bhim Sain

doi:10.1007/978-981-15-8297-4_50

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Figure 1 Subthreshold Leakage Of Nmos1

Forced Stack1

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2022

2024

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Cited by 3 publications

(2 citation statements)

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“…For reducing this oxide leakage current high k dielctric materials can be used. For reduction in static power, sleepy stack architecture has been used in this paper, which combines advantages of two techniques i.e sleep transistor and forced stack [18][19][20].…”

Section: Figure 1 Subthreshold Leakage Of Nmosmentioning

confidence: 99%

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Implementation and Modeling of Low Power Sleepy Stack Sram

Kakkar¹

2022

joas

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For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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Section: Figure 1 Subthreshold Leakage Of Nmosmentioning

confidence: 99%

“…Figure 4 shows the forced stack inverter containing two pull-up and pull-down transistors [27]. As this cell has two bitlines (bitline and bitline'), depending upon the value which is stored in SRAM cell, leakage current differs [18]. Bitline leakage accounts 35% of SRAM leakage power consumption.…”

Section: Forced Stackmentioning

confidence: 99%