Design of A 1.5-V 3-5 GHz CMOS Low-Voltage Transformer-Based Low Noise Amplifier with TR Switch for Computational Intelligence Applications

Lai, Wen Cheng; Su, Yongbo

doi:10.1109/iscid.2016.2068

Cited by 2 publications

(1 citation statement)

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“…Instead of that, current reuse technology and sub-threshold operations are recommended to reduce the power consumption of the circuit [5,6]. Implementing stagger tuning technique and resistive shuntfeedback configuration can increase the bandwidth [7][8][9]. While considering the NF and power dissipation, stagger tuning technique is better to achieve wideband.…”

Section: Introductionmentioning

confidence: 99%

Design and optimisation of feedforward noise cancelling complementary metal oxide semiconductor LNA for 2.4 GHz WLAN applications

Roobert¹,

Rani²,

Rajaram³

2019

IET Circuits, Devices & Systems

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This study deals with the design and optimisation of two-stage complementary metal oxide semiconductor low noise amplifier (LNA) for wireless local area network (WLAN) applications. IEEE 802.11n WLAN standard provides up to 600 Mbps speed with 40 MHz channel bandwidth and high throughput. The receiver of these WLAN applications requires LNA with higher gain and minimum noise figure (NF). Elephant Herding Optimisation technique was involved for the first time to optimise the performance of the LNA. The post-layout simulation shows that a maximum gain of 26.7 dB at 2.4 GHz is achieved in the proposed design. Feedforward noise cancelation technique is involved to get a reduced NF of 1.12 dB. The first and second stages are tuned to cover the 3 dB maximum gain bandwidth of 3.2 GHz (from 1.7 to 4.4 GHz). This LNA is designed at 90 nm technology with the supply voltage of 0.5 and 1.2 V, and consumes 8.9 mW of power. Current reuse technology is used to reduce power consumption. The input and output return losses have been found to be −18 and −15 dB, respectively at the targeted 2.4 GHz frequency. Third-order input intercept point of the optimised LNA is −8.1 dBm.

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