Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

Abstract

SUMMARY This paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz fT, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley & Sons, Ltd.

Time‐interleaved SAR ADC design with background calibration

“…Thus, the sampling capacitance is determined 80 F. Kick-back noise is another important noise contributor in ADC circuits. To lower kick-back noise, input buffer is generally preferred option, 21,22 but it comes with power penalty. In our circuit, input capacitance is small, which eliminates the necessity of using buffer.…”