Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Abstract

This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 µm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are ( 0/ + 0.63 ) LSB and ( −0.26/ + 0.31 ) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Darlington CMOS İnverter Tabanlı Paralel Analog-Sayısal Dönüştürücü Tasarımı

“…Bu yüzden paralel analog-sayısal dönüştürücülerin en önemli bloklarından birisi olarak tanımlanır [4]. Çünkü sistemin band genişliğini, analog giriş gerilim aralığını ve güç tüketimini etkileyen en önemli bloklardan birisidir [10,11]. Bu yüzden literatürde karşılaştırıcı devresi olarak kullanılan birçok yapı mevcuttur.…”

“…Darlington cmos inverter tabanlı karşılaştırıcı bloğu dc sonuçları.2.2 Sayısal Kod Çözme Bloğu ( Digital Encoder Block)Sayısal kod çözme bloğu; dinamik tutucu devresi, 1-n kodlayıcı ve pla-rom bloğundan oluşmaktadır. A/S dönüştürücü tasarımlarında analog ve sayısal bloklar arasında ki kontrolü sağlamak için dinamik tutucu devresine ihtiyaç vardır [10,29]…”

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

“…Depending on the clock signal, either the logic value of former input signal is kept at the output or the logic value of current input signal is transmitted to the next stage of the ADC. Thus, digital part of the ADC is somehow relaxed for accurate conversion, because of continuous change of the analog input signal [32,33]. In other words, when the clock signal is logic "0", it means that the analog input is sampled at this time; however, when the clock signal is logic "1" it means that the digital conversion of that sample is executed in the digital part of the converter.…”