Design of a C-testable booth multiplier using a realistic fault model

Sas, J. van; Nowé, Chay; Pollet, Didier; Catthoor, Francky; Vanoostende, P.; Man, H. De

doi:10.1007/bf00971961

Cited by 10 publications

(8 citation statements)

References 16 publications

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“…The testability of multipliers based on the modifiedBooth algorithm, in the restrictive case when the structure of most or all of its cells was known, was examined in [16][17][18]. In [16] the test set for a multiplieraccumulator based on the modified-Booth algorithm was given requiring the addition of 2 extra primary inputs.…”

Section: Introductionmentioning

confidence: 99%

“…Extra hardware is required for the Ctestable design and the required extra primary inputs are 3. In [17] the specific cell implementations of another silicon compiler, namely Cathedral [20] were used. The fault model used in [ 17] includes node stuckat, transistor stuck-open and stuck-close faults for the specific cell implementations which include symmetric but also non-symmetric CMOS gates.…”

Section: Introductionmentioning

confidence: 99%

“…In [17] the specific cell implementations of another silicon compiler, namely Cathedral [20] were used. The fault model used in [ 17] includes node stuckat, transistor stuck-open and stuck-close faults for the specific cell implementations which include symmetric but also non-symmetric CMOS gates. Three extra primary inputs are needed to make the multiplier C-testable with a test set of 50 test patterns.…”

Section: Introductionmentioning

confidence: 99%

“…For the specific DCVS implementations of the multiplier cells, the multiplier is C-testable with 31 test patterns, detecting all detectable single stuck-at, stuck-on and stuck-open faults, when 6 extra primary inputs, 2 extra primary outputs and some extra logic are added. In [16][17][18] the hardware and delay overheads were not explicitly calculated.…”

Section: Introductionmentioning

confidence: 99%

“…The proposed design is Ctestable with 61 test vectors when the former is used and with 73 test vectors when the latter is used. At this point we remark that the C-testable designs proposed in [16][17][18]21] consider only the use of ripple carry adders at the last stage of the multiplication.…”

Section: Introductionmentioning

confidence: 99%

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C-Testable modified-Booth multipliers

et al. 1996

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In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an Nx x Ny bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%