Design of a Current Sensor for IDDQ Testing of CMOS IC

Ali, Mohd Liakot; Khamis, Nurul Huda

doi:10.3844/ajassp.2005.682.687

Cited by 6 publications

(4 citation statements)

References 6 publications

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“…When the quiescent state current is greater than the reference current, the output signal PASS/FAIL is set to 1, which indicates the existence of fault in the circuit. When the quiescent state current is less than the reference current, the output signal PASS/FAIL is set to 0, which indicates the nonexistence of fault [21]- [24].…”

Section: Design Consideration Of Bicsmentioning

confidence: 99%

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Kaur¹,

Kaur²

2018

IJECE

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The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using n-well 0.18µm CMOS technology.

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Section: Design Consideration Of Bicsmentioning

confidence: 99%

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Kaur¹,

Kaur²

2018

IJECE

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“…The width for the CMOS devices are chosen based on designed equations (Allen and Holberg, 2002;Ali and Khamis, 2005;Nabhan and Abdallah, 2010). The supply voltage of the Op amp is chosen ±1.2V for reducing power consumption.…”

Section: Methodsmentioning

confidence: 99%

Design of Capacitance to Voltage Converter for Capacitive Sensor Transducer

Helén¹

2010

American Journal of Applied Sciences

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Problem statement:The design of Capacitance to Voltage Converter (CVC) for capacitive sensor transducer was presented. The proposed design will reduce the size, power consumption and supply voltage of the circuit and can be used in high frequency band transducer. Approach: The design was implemented using the Operational amplifier (Op amp) and capacitive network. The circuit was simulated using the PSPICE model parameters based on standard 0.13 µm CMOS process. Results: The design was able to measure a wide range of capacitance variations for the capacitive transducer. The performance analysis of the design showed desirable performance parameters in terms of response, low power consumption and a linear output voltage within the wide range of capacitive transducer capacitance variation for the power supply voltage of 1.2 V was achieved. Conclusion/Recommendations: The output voltage of the circuit varied linearly with the variation of capacitive transducer capacitance variation. The improved converter was compact and robust for integration into capacitive measuring systems and suitable for use in environment that making use of higher frequency band.

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“…The purpose of the electrodynamics sensor is to capture the electrical charge from the conveyed material such as plastic beads that pass through the sensor/transducer (Furati et al, 2005;Ali and Khamis, 2005;Addasi, 2005). The electrodynamics sensor consists of a plain metal rod called electrode, which is isolated from the walls of the metal conveying pipe by an insulator e.g.…”

Section: Electrodynamics Sensormentioning

confidence: 99%

Image Reconstruction Algorithm for Electrical Charge Tomography System

Rahmat¹,

Isa²,

Jusoff³

et al. 2010

American Journal of Applied Sciences

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Problem statement: Many problems in scientific computing can be formulated as inverse problem. A vast majority of these problems are ill-posed problems. In Electrical Charge Tomography (EChT), normally the sensitivity matrix generated from forward modeling is very ill-condition. This condition posts difficulties to the inverse problem solution especially in the accuracy and stability of the image being reconstructed. The objective of this study is to reconstruct the image cross-section of the material in pipeline gravity dropped mode conveyor as well to solve the ill-condition of matrix sensitivity. Approach: Least Square with Regularization (LSR) method had been introduced to reconstruct the image and the electrodynamics sensor was used to capture the data that installed around the pipe. Results: The images were validated using digital imaging technique and Singular Value Decomposition (SVD) method. The results showed that image reconstructed by this method produces a good promise in terms of accuracy and stability. Conclusion: This implied that LSR method provides good and promising result in terms of accuracy and stability of the image being reconstructed. As a result, an efficient method for electrical charge tomography image reconstruction has been introduced.

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Design of a Current Sensor for IDDQ Testing of CMOS IC

Cited by 6 publications

References 6 publications

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

Design of Capacitance to Voltage Converter for Capacitive Sensor Transducer

Image Reconstruction Algorithm for Electrical Charge Tomography System

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