Design of a Data Recovery Block for Communications over Power Distribution Networks of Microprocessors

Abstract

We proposed the use of power distribution network (PDN) of a microprocessor for ubiquitous access of internal nodes for test/debug and showed the suitability of impulse ultra-wideband (UWB) communications for the purpose. This paper presents design of a data recovery block to recover data from UWB impulses superposed on a power line of a microprocessor. Considerations for data recovery block design based upon measured PDN characteristics have been discussed. The proposed circuit was implemented in TSMC 0.18 um CMOS process, and simulations show that it consumes 4.42 mW when operating from a 1.8V supply and at a pulse repetition rate of 200 MHz.

Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

“…Transient simulations indicate that the PLC receiver can recover data from impulses with the amplitude of ∼90 mV and the period of 300 ps superimposed on the supply voltage of 1.8 V. The pulse repetition rate of the impulses is 1 GHz. A PLC receiver based on a correlator is reported in [26], and its improved version is reported in [27]. Another PLC receiver based on a differential Schmitt trigger is presented in [29].…”