Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Brito, Juan Pablo Martinez; Bampi, Sérgio

doi:10.1007/s10470-008-9184-7

Cited by 10 publications

(1 citation statement)

References 27 publications

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“…Two DCOs were required to extend the multiplication range and operational frequency [5]. Compared to the conventional clock generators [1][2][3][4][5][6][7][8][9], overall hardware complexity can be decreased for the high jitter performance and timing resolution.…”

Section: Introductionmentioning

confidence: 99%

All-digital PLL using bulk-controlled varactor and pulse-based digitally controlled oscillator

Huang

Liu

2011

Analog Integr Circ Sig Process

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This work presented a 150-450-MHz, all-digital phase-locked loop (ADPLL) implemented in a 0.18 lm CMOS process. The design utilizes bulk-controlled varactor and pulse-based digitally controlled oscillator (PB-DCO) providing a high timing resolution and a good jitter performance. The worst-case total locking time of the proposed ADPLL is 32 reference clock cycles. The divider used here divides by factors from 2 to 63. A test chip is implemented and verified. The RMS and peak-to-peak jitters are 6.7 and 44 ps, respectively, at 450-MHz. The peak-to-peak jitter is 2.0% at 450-MHz. When the multiplication of divider is varying at 150-MHz, the peakto-peak jitters are less than 3.2%. The power consumption is 16.2-mW at 450-MHz. The core area of ADPLL is only 260 9 360 mm 2 . This clock generator can be applied as re-usable silicon IP for system-on-chip (SoC) applications.

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