Design of a dynamic depth high-throughput multi-clock FIFO for the DSPIN

Abstract

The clock distribution within ChipMultiprocessors(CPMs) and System-on-chips (SoCs) come to be difficult as the number of processing elements increasing and the communication between those components are becoming even more critical. In recent years, researchers proposed Globally Synchronous Locally Synchronous (GALS) clocking scheme to reduce clock skew, power, and energy consumption in CPMs and SoCs. In this paper we have demonstrated dynamic depth multi-synchronous first-in first-out (FIFO) buffer which is useful for transferring data between two processing elements within a Distributed Scalable Predictable Interconnect Network(DSPIN).It also demonstrates dynamic calculation of FIFO depth using two clock frequency and packet size of in coming data.

Design of Ethernet-VLC Data Conversion System Based on FPGA

“…Depth calculation is very important to pass the data between different clock domains [16]. In downlink the deeper FIFO depth is better to use in speed-down buffer.…”