Design of a dynamically programmable logic gate

Suarez, Ricardo E.; Chang, Oscar; Adam, Vladimir

doi:10.1109/tc.1981.6312160

Cited by 2 publications

(1 citation statement)

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“…This is a well-known fact in electronics where it has been one of the main battle-horses almost since the beginning of computer architecture [13], Although several equivalent configurations have been reported also in photonics, its use is not so widespread. The one presented here was reported previously by us [15], the design and the used devices being the main difference with the previous ones.…”

Section: Optical Computing Logic Cellmentioning

confidence: 99%

Analysis of irregular behaviour on an optical computing logic cell

González-Marcos

Martin-Pereda

2000

Optics & Laser Technology

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A new methodology to study irregular behaviours in logic cells is reported. It is based on two types of diagrams, namely phase and working diagrams. Sets of four bits are grouped and represented by their hexadecimal equivalent. Some hexadecimal numbers correspond to certain logic functions. The influence of the internal and external tolerances, namely those appearing in the employed devices and in the working signals, may be analysed with this method. Its importance in the case of logic structures with chaotic behaviours is studied.

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Section: Optical Computing Logic Cellmentioning

confidence: 99%

Analysis of irregular behaviour on an optical computing logic cell

González-Marcos

Martin-Pereda

2000

Optics & Laser Technology

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Design of error-tolerant cache memory for multithreaded computing

Wang

2008

2008 IEEE International Symposium on Circuits and Systems

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With the trend towards nanometer billion-transistor integration, reliable computing becomes increasingly challenged by semiconductor process variations and low-level physical effects. This is particularly a problem for on-chip memory circuits. In this paper, we propose an error-tolerant memory design technique based on a unique phenomenon referred to as the inter-thread transient redundancy in multithreaded computing. A new memory microarchitecture is developed that exploits dynamic mapping strategies for compensation of unpredictable performance variations and soft errors. Trace driven simulations on the SPEC CPU2000 benchmarks show the advantages of the proposed technique for improving error tolerance in multithreaded microprocessors.

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Design of a dynamically programmable logic gate

Cited by 2 publications

References 1 publication

Analysis of irregular behaviour on an optical computing logic cell

Analysis of irregular behaviour on an optical computing logic cell

Design of error-tolerant cache memory for multithreaded computing

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