Design of a good oscillation frequency and moderate phase noise current mirror VCO

Rout, Shasanka Sekhar; Acharya, Satabdi; Sethi, Kabiraj

doi:10.1016/j.procs.2020.04.095

Cited by 2 publications

(2 citation statements)

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“…They found white noise during the delay stage and flicker noise during the tuning stage. Routh et al [11] presented a VCO concept that uses a current mirror to increase drain current. They focused on low-power noise and swing amplitude.…”

Section: -Literature Reviewmentioning

confidence: 99%

“…Equations 6 to 8 give the negative skewed component of the circuit's delay. Equations (11) Figure 12 depicts the proposed architecture implemented using LTspice to acquire the results of waveform, rapid Fourier transform, harmonic distortion, and harmonic frequencies. LTspice reports revealed additional frequency divisions and components.…”

Section: Figure 11 Schematic Of Proposed Designmentioning

confidence: 99%

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Design and Study the Performance of a CMOS-Based Ring Oscillator Architecture for 5G Mobile Communication

Rahman,

Kishore,

Abdul Rajak

2024

Emerg Sci J

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Oscillator circuits are used to make accurate and reliable clock signals for systems as simple as a wristwatch and as complicated as satellites, which are important for long-distance communication. There are many ways to build an oscillator circuit, using either passive or active parts. Each option has pros and cons, but at the current level of mobile communication development, the most important things are interoperability and low power use. This need has driven the development of compact, battery-operated electronics, and Very Large-Scale Integration (VLSI)-based ring oscillators provide the ideal solution. These oscillators ought to dissipate less power, have a large tuning range, and be compact. The paper presents a novel Complementary Metal Oxide Silicon (CMOS) ring oscillator that serves as a Voltage Controlled Oscillator. The suggested architecture utilizes the advantages of both a current-starved ring oscillator and a negative-skewed delay by combining their constituent parts. The proposed architecture has a control voltage of 1.15 V and a supply voltage of 2 V, generating a 9.35 GHz dominant frequency with a 13.82% harmonic distortion between the inputs and outputs. The proposed architecture can implement 5G-based applications that require high frequency and low power by carefully selecting the passive components within the design. Doi: 10.28991/ESJ-2024-08-01-020 Full Text: PDF

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Section: -Literature Reviewmentioning

confidence: 99%

Section: Figure 11 Schematic Of Proposed Designmentioning

confidence: 99%