Design of a Hamming neural network based on single-electron tunneling devices

Guimarães, Janaína Gonçalves; Nobrega, L. M.; Costa, J.C. da

doi:10.1016/j.mejo.2005.07.007

Cited by 11 publications

(16 citation statements)

References 17 publications

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“…Finally, other bit maps with increased Hamming distances could be used to enhance discrimination between patterns. 3 We consider now a possible practical realization for scheme 2. It has been shown experimentally that the drain-to-source current through a nanosystem array is close to zero for V d < V th and follows a power law with V d for V d > V th 6,34 (see Figure 8a here and Figure 2 .…”

Section: Resultsmentioning

confidence: 99%

“…These potentials are the inputs to the CMOS winner-take-all (WTA circuit), which selects that particular array, k, whose capacitor voltage, V k , reaches a prescribed voltage more rapidly. 2,3 This should correspond to the stored number with the lowest HD with respect to the input number (see Figure 2): the higher the number of bit coincidences between the input and the stored number, the higher the number of basic units in states of high conductance (see eq 1) and, therefore, the higher the capacitor charging current through the array (see Figure 3b). …”

Section: Introductionmentioning

confidence: 99%

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Associative Memory Based on Double-Gating of Molecularly Linked Nanosystem Arrays: A Theoretical Scheme

2008

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We discuss theoretically the properties of an associative memory (a system that can retrieve a stored pattern that is similar to the input pattern) based on the ideal conductive properties of a molecularly linked nanosystem array. Two schemes are considered for the memory based on the gate potential modulation of the drainsource current through the array. In the first scheme, the basic units of the electric circuit are nanosystems (e.g., nanoparticles) arranged in a series array. Each nanosystem is assumed to have two states of conductances, G M and G m (G M . G m ), that can be tuned externally by the gate and backgate potentials. The bit sequence associated with a given pattern is stored as the components of a voltage vector. The input vector components are the gate voltages, and the stored vector components are the backgate voltages. The input pattern is compared with a given stored pattern by double-gating each nanosystem in the array with the respective components of the two vectors (the number of arrays is equal to the number of patterns to be stored). The individual conductances of the nanosystems in the array are high (G M ) when the input and stored vector components (bits) are equal and low (G m ) when they are different. The basis of the pattern recognition process is that the higher the number of bit coincidences, the higher the number of nanosystems in the array that are in states of high conductance and, therefore, the higher the drain-to-source current through the array. Alternatively, we consider also the properties of a second scheme in which the basic unit to be double-gated is the nanosystem array as a whole rather than a single nanosystem. Candidate experimental systems and simple circuit equations are considered for the two schemes that constitute preliminary steps toward future realizations of the associative memory using particular nanosystem arrays.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Associative Memory Based on Double-Gating of Molecularly Linked Nanosystem Arrays: A Theoretical Scheme

2008

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“…Capacitance and junction values of the single-electron Hamming network used in this recognition task are the same used in a previous work (22). These values are shown in Table 1 …”

Section: Simulation Parametersmentioning

confidence: 99%

Image Recognition Task Based on Decoupled Single-Electron Hamming Networks

2007

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This paper presents a black and white image recogniton task implemented using a decoupled single-electron (SET) Hamming neural network. For the first time, more than 18000 single-electron transistors are used in such a task. This network allows a more practical hardware implementation. Simulation results for various temperatures are presented. A vector clustering task is simulated using SIMON. Robustness against random offset charges, as well as dynamic behavior are evaluated.

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“…[3][4][5] Among all neural networks existing today, this paper focuses on the Hopfield neural network, 6 which is a recurrent neural network. This network works as a Content-Addressable Memory (CAM), which addresses the input parameters of a circuit based on the information stored in its structure.…”

Section: Introductionmentioning

confidence: 99%

Pattern Recognition Based on Auto-Associative Single-Electron Neural Network

Nogueira¹,

Guimarães²

2012

j comput theor nanosci

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This paper presents a pattern recognition task based on an auto-associative neural network using single-electron tunnelling (SET) devices. The nanoelectronic network is able to converge to a pattern previously stored during training. The operation of the circuit is verified using simulation, operating at 0 K and at room temperature. The effects of increasing the temperature of the neural network circuit is analyzed. The pattern recognition involves decreasing the energy of the input state until it achieves a point of local minimum energy. The task of minimizing the energy of the nanoelectronic system associated with characters is shown for the first time.

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Design of a Hamming neural network based on single-electron tunneling devices

Cited by 11 publications

References 17 publications

Associative Memory Based on Double-Gating of Molecularly Linked Nanosystem Arrays: A Theoretical Scheme

Associative Memory Based on Double-Gating of Molecularly Linked Nanosystem Arrays: A Theoretical Scheme

Image Recognition Task Based on Decoupled Single-Electron Hamming Networks

Pattern Recognition Based on Auto-Associative Single-Electron Neural Network

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