Design of a high information-density multiple valued 2-read 1-write register file

Abstract

Abstract:In this paper, a multiple valued register file (MVRF) with 2-read 1-write circuit is designed in TSMC Low Power 65 nm CMOS. High V TH and Low V TH transistors are organized together to realize a multiple-threshold Literal Gate, and then connect with pass-gates to implement ternary valued register file cell. The information density of the proposed MVRF cell achieves a 61% improvement compared to a standard 6T SRAM, and more than 140% improvement compared to a binary register file. In addition, the quantity of the word line and bit line reduces about 33% compare to a standard 6T SRAM, which also improves the system information density. An 8 × 8 MVRF array have been designed and simulated in terms of power, speed and cell stability. Simulation results show that the MVRF array operates at 1.0 GHz, consuming 1.2 mW at 1.2 V.

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

“…Ternary SRAM is an alternative technology to binary SRAM for enlarging the SRAM storage capability and improving performance. For example, a 10 × 10 ternary SRAM has about the same SRAM storage capability as a 16 × 16 binary SRAM [2] ; in the ternary SRAM systems, the number of the wordline and the bitline reduce by about 33% compared to the standard 6T SRAM [3] . However, the implementation of a compact CMOS ternary SRAM requires the utilization of additional bias voltages [1] , thus increasing the complexity of the power grid and producing poor area efficiency.…”