Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders

Tari, Hani Taheri; Zarandi, Arezoo Dabaghi; Reshadinezhad, Mohammad Reza

doi:10.1016/j.mee.2019.110980

Cited by 23 publications

(11 citation statements)

References 25 publications

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“…The additional multiplexer is used in Stage III to produce the final output carry. If Cin='0', it selects the final carry of stage I i.e., C1 [3]; when Cin='1', the final carry produced in Stage II i.e., Ce1 [3] will be the output carry.…”

Section: Stage IImentioning

confidence: 99%

“…This design replaces the second stage of CaSeA with a binary to excess-1 converter. Few previous works such as [1] and [3] focused on the design of efficient full adder which would be used in CaSeAs. The authors of [3] proposed a novel CNTFET-based full adder at 32nm CNFET technology for various parallel adders and their impact on large computing systems.…”

Section: Introductionmentioning

confidence: 99%

“…Few previous works such as [1] and [3] focused on the design of efficient full adder which would be used in CaSeAs. The authors of [3] proposed a novel CNTFET-based full adder at 32nm CNFET technology for various parallel adders and their impact on large computing systems. Carry propagation time can also be minimized by introducing carry-propagation and carry-generation i.e., Carry Look-Ahead adder (CLAA).…”

Section: Introductionmentioning

confidence: 99%

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A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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This paper proposes a novel architecture of novel excess-1 adder basedCarry Select Adder (M2CSA) using single leaf cell i.e., 2-1 Multiplexer. The proposed4-, 8-, 16-, 32-, 64-bit M2CSAs use 2-1 Multiplexers only. The complex gates suchas XOR gates are completely eliminated which exist in existing Carry Select Adders(CaSeAs). A 64-bit M2CSA is distinctly decomposed for maintaining excellent cellregularity that uses one type of 2-1 Multiplexer cell. Ripple carry adder block inexisting designs are replaced with half adders by reducing the carry propagation tocertain extent. At the outset the speed of M2CSA is improved by overcoming carrypropagation through adder blocks, especially in 32- and 64-bit adders. The area isthe major concern for CaSeAs; is also reduced for M2CSAs by maintaining the cellregularity. The M2CSA and existing CaSeAs are designed using Verilog HDL. Thefunctional testing of all the designs is carried out using Cadence NCLaunch. All thedesigns are synthesized & implemented using Cadence Genus and Innovus respectivelyat 90nm technology node. The final ASIC layout of 64-bit M2CSA is more compact interms of area by an average of 17% compared to existing designs. The result analysisand comparison reveal that M2CSAs are better in terms of speed and power dissipationby 20% and 19% respectively. Therefore, M2CSA is best suitable to low-power, low area and high-speed applications

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Section: Stage IImentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

Battini

Bikshalu²,

Sivani³

2023

Eng. Res. Express

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“…where a is the inter-carbon-atom distance of approximately 0.249 nm [4]. The V th is determined by Equation 2:…”

Section: Cntfet Technology and Mvl Circuits Review A Carbon Nanomentioning

confidence: 99%

“…Complementary Metal Oxide Semiconductor (CMOS) technology faces major problems such as short channel effects [1], high current leakage, decreasing gate control and high lithography costs, etc., when scaled down near to nanometers [1]. Scientists and researchers seek to find alternatives to the traditional CMOS process [2]- [4], to overcome the above mentioned problems.…”

Section: Introductionmentioning

confidence: 99%

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

2020

Self Cite

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The huge quantity of nodes and interconnections in modern binary circuits leads to extremely high levels of energy consumption. The interconnection complexity and other issues of binary circuits encourage researchers to consider multiple-valued logic (MVL) alternatives. Features of Carbon Nanotube Field-Effect Transistors (CNTFETs) make this technology a potential candidate to implement MVL circuits. In this article, a new systematic methodology is proposed to design ternary logic block circuits based on CNTFETs. The methodology is applied to the design of two basic logic circuits, a half adder and a 1-digit multiplier, which are evaluated through HSPICE simulations. Simulation results indicate improvements over current equivalents in transistor count and PDP mean with the half adder version of 19.2%, and 74.07% respectively, and with the 1-digit multiplier of 24.67% and 81.12% respectively.

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High-Speed Less Area CNTFET Ternary Half Adder Using Pseudologic

Divya

Gowthami

Musala

2023

Lecture Notes in Networks and Systems

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Design of a high performance CNTFET-based full adder cell applicable in: Carry ripple, carry select and carry skip adders

Cited by 23 publications

References 25 publications

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells

High-Speed Less Area CNTFET Ternary Half Adder Using Pseudologic

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