Design of a High-Reliability FPGA Platform for High-Resolution Image Process System

Abstract

With continuous advancement in science and technology, the image quality has entered an era of full-HD. This study developed a high-reliability image processing system platform, based on the FPGA platform. By using a high-reliability hardware platform development process, and with the aid of the simulation software, this study simulated the transmission integrity of the high-speed digital signals on the PCB. The proposed method was used to build a FPGA-based high-reliability image processing system platform. The implementation in this study, with the length of the Clock and DQS signal line of DDR2 being controlled within 555 mil, was discussed, and the errors were analyzed. The simulated value of the tDQSCK was 195.048 ps, the measured value was 215 ps, and the standard value of the JEDEC was less than 350 ps. Between the simulated value and the measured value, there was only an error of about 9.3%, which meets the reliability requirement. The length tolerance of the signal line laid was 38.5% better than the standard value of the JEDEC.