Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications

Abstract

For high-speed operations, low power consumption and small silicon area, transistors are being scaled aggressively. Meanwhile, circuit reliability is facing greater challenges in advanced technologies. In this paper, a highly reliable and lowpower SRAM with double-node-upset (DNU) recovery, namely HRLP16T, is proposed for safety-critical fields. HRLP16T can recover from single-node-upset (SNU) at all the sensitive nodes, and it has eight node pairs recover from DNUs. Simulationbased evaluation results demonstrate advantages in terms of delay and power consumption over epical existing SRAM cell designs.