2019 2nd International Conference on Innovation in Engineering and Technology (ICIET) 2019
DOI: 10.1109/iciet48527.2019.9290624
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Design of a Linearized Split-Load Low Power Single-Ended Ring Oscillator with High Tuning Range

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Cited by 1 publication
(2 citation statements)
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“…A three stage SERO with load capacitances is simulated in 90 nm technology using Cadence Virtuoso platform. The supply voltage is varied between 0.3 V and 2 V. The value of the load capacitance is calculated using the equation in [12]. The circuit is first simulated with Rw = 2 and the new equation is compared with the conventional equations.…”
Section: Simulation Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…A three stage SERO with load capacitances is simulated in 90 nm technology using Cadence Virtuoso platform. The supply voltage is varied between 0.3 V and 2 V. The value of the load capacitance is calculated using the equation in [12]. The circuit is first simulated with Rw = 2 and the new equation is compared with the conventional equations.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…In a similar method as before, the integral limits are now from 0 to VDD and VDD to 0 for equations (3) and (4), respectively. The propagation delays then obtained are given by (11) and (12) which leads to the frequency equation given by (13). This is the most common equation in literature.…”
Section: A Current Source (Cs) Model 1) Delay At 50% Levelmentioning
confidence: 99%