Design of a low power Digital Down Converter for 802.16m - 4G WiMAX on FPGA

Rupanagudi, Sudhir Rao; Bhat, Varsha G.; Hemalatha, S.; Bhavana, N; Archana, M S; Chandrika, B V; Ashwini, R; Torvi, Keerti G.; Darshan, S; Abhilash, B; Anil, Kumar S; Swamy, K M Vinayak

doi:10.1109/icacci.2014.6968583

Cited by 8 publications

(3 citation statements)

References 14 publications

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“…Since its inception the communication fields have been noticed many enhancements. Some of the reasons behind it are the requirements of good design, efficiency of power and area [1]. In communication devices the most important block is numerically controlled oscillator (NCO).…”

Section: Introductionmentioning

confidence: 99%

Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator

Gujjula

Perumal²,

Kodali³

et al. 2023

IJRES

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The numerically controlled oscillator (NCO) is one of the digital oscillator signal generators. It can generate the clocked, synchronous, discrete waveform, and generally sinusoidal. Often NCOs care utilized in the combinations of digital to analog converter (DAC) at the outputs for creating direct digital synthesizer (DDS). The network on chips (NOCs) are utilized in various communication systems that are fully digital or mixed signals such as synthesis of arbitrary wave, precise control for sonar systems or phased array radar, digital down/up converters, all the digital phase locked loops (PLLs) for cellular and personal communication system (PCS) base stations and drivers for acoustic or optical transmissions and multilevel phase shift keying/frequency shift keying (PSK/FSK) modulators or demodulators (modem). The basic architecture of NCO will be enhanced and improved with less hardware for facilitating complete system level support to various sorts of modulation with minimum FPGA resources. In this paper design and memory optimization of hybrid gate diffusion input (GDI) numerically controlled oscillator based on field programmable gate array (FPGA) is implemented. compared with NCO based 8-bit microchip, memory optimization of hybrid GDI numerically controlled oscillator based on FPGA gives effective outcome in terms of delay, metal-oxide-semiconductor field-effect transistors (MOSFET’s) and nodes.

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Section: Introductionmentioning

confidence: 99%

Design and memory optimization of hybrid gate diffusion input numerical controlled oscillator

Gujjula

Perumal²,

Kodali³

et al. 2023

IJRES

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“…et al,2013) and implemented a Vedic Mathematics multiplier on FPGA. Since then, several authors have been implementing Vedic Mathematics based multipliers in several applications related to the fields of communication, cryptography and DSPs (S. R. Rupanagudi et al,2014;S. Rao Rupanagudi et al, 2019).…”

Section: Introductionmentioning

confidence: 99%

Design of 128-bit Complex Number Multipliers for Co-Processor

Panda¹

2020

Biosci. Biotech. Res. Comm

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Multipliers are the backbone of high-performance computing systems such as Microprocessors and Digital signal processors. Multipliers require more hardware resources and processing time, hence they are the slowest elements in the system. Multipliers are mainly used in today's high-end Digital Signal Processors and they occupy a larger chip area because of their inherent internal circuit complexity. Present-day co-processors are designed to support different size computations to achieve high performance. Researchers have worked on signed and complex number multipliers used in co-processors of 64 bit and below. There is a scope for designing a higher bit complex number multiplier to achieve higher performance. In this context, we proposed to design of 128-bit complex number multiplier of various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier using ModelSim SE 6.4 and Xilinx Vivado. In this work, various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier for 8-bit, 16-bit, 32-bit, 64-bit and 128-bit designed using Verilog for complex number multiplication. Nikhilam is one of the sutras of Vedic mathematics which is chosen for the implementation of complex number multiplier for area reduction. Synthesis reports are generated using the Xilinx Vivado tool for speed and power comparison. From the comparison, we have observed that Booth, Modified Booth, Urdhva, and Nikhilam occupy an area of 324.32%, 292.79%, 56.36%, and 46.70% respectively for 128-bit implementations. Among all the implemented methods, the Nikhilam method for complex number multiplier occupies very less area i.e. only 46.70% on-chip area.

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“…NCO generates sine samples, which are multiplied with the incoming IF signal. The output of the mixer is then fed to a chain of decimating filters, to reduce the sampling rate of the signal as well as to filter out the spectral replications obtained during multiplication of incoming and carrier signals to attain baseband spectrum of interest [10].…”

Section: Introductionmentioning

confidence: 99%