Design of a low power wide-band high resolution programmable frequency divider

Yu, Xiaopeng; Do, M.A.; Jia, Lin; Ma, Jan; Yeo, Kiat Seng

doi:10.1109/tvlsi.2005.857153

Cited by 37 publications

(16 citation statements)

References 8 publications

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“…When the state "0000" is reached, MOD goes high, M 6 is turned-on and M 7 is turned-off such that node S1 and S2 remain at logic '0' for the remaining N*(P-S) clock cycles until LD becomes high. During this period, since LD='0', the right hand side portion of the circuit is de-activated similar to the reloadable DFF reported in [11]. Thus there is no switching activity at any node during the idle state of the S-counter and switching power is saved for a period of N*(P-S) clock cycles.…”

Section: Swallow S-countermentioning

confidence: 72%

“…12. It consists of proposed 6 asynchronous reloadable bit-cells [11], a NOR-embedded DFF [12] and an end-of-count (EOC) detector with reload circuit.…”

Section: Programmable P-countermentioning

confidence: 99%

“…Fig.14 shows the schematic of an improved reloadable TSPC DFF used in the design of 6-bit S-counter. This reload DFF is similar to the reloadable DFF used in the design of P-counter [11]. However, the reloadable DFF for the S-counter needs an extra logic function MOD to be incorporated.…”

Section: Swallow S-countermentioning

confidence: 99%

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A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Krishna

Xie

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

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Abstract. This paper presents a low power 2.4-GHz fully integrated 1 MHz resolution IEEE 802.15.4 frequency synthesizer designed using 0.18um CMOS technology. An integer-N fully programmable divider employs a novel Truesingle-phase-clock (TSPC) 47/48 prescaler and a 6 bit P and S counters to provide the 1 MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 uW. The S-QVCO consumes 2.8 mW of power with a phase noise of -122dBc/Hz at 1 MHz offset. IntroductionMost of the wireless communication standards prior to IEEE 802.15.4/Zigbee were tailored towards high data rate and multimedia friendly applications. The need for low data rate and low power wireless solutions with emphasis on sensor network applications resulted in the development of IEEE 802.15.4 standard. The recent development and advanced scaling CMOS technologies have made it more attractive to implement a single chip CMOS wireless transceiver featuring both high level of integration and low power consumption [1]. The higher power consumption in the frequency synthesizer is mainly due to the VCO and the first stage divider which is driven by the VCO. The 2.4 GHz synthesizer reported in [2] with a frequency resolution of 5 MHz consumes a power of 7.85 mW at 1.8 V power supply in 0.18 um CMOS technology. Here, the first stage divider is designed using current-mode logic (CML) [6] which consumes a large amount of power. The synthesizer reported in [3] consumes 2.4 mW at 1.2 V supply in 0.13 um CMOS technology. It uses a 16/17 dynamic logic prescaler as first stage divider which consumes only 176 uA at 2.5 GHz and the complete divider is designed with 5

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Section: Swallow S-countermentioning

confidence: 72%

“…12. It consists of proposed 6 asynchronous reloadable bit-cells [11], a NOR-embedded DFF [12] and an end-of-count (EOC) detector with reload circuit.…”

Section: Programmable P-countermentioning

confidence: 99%

See 1 more Smart Citation

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

Krishna

Xie

et al. 2012

VLSI-SoC: Forward-Looking Trends in IC and Systems Design

View full text Add to dashboard Cite

show abstract

“…It consists of three asynchronous loadable bit-cells, a DFF and logic gates to achieve programmability from 0 to 7. The asynchronous loadable bit-cell, as shown in Figure 3 is similar to the bit-cell reported in [7], except the five transistors M1 M5 M6 M9 M14 whose inputs are controlled by the logic signal SP or SPB. SPB is inversed to SP and when SP is switched to logic '1', S-counter stops counting.…”

Section: Programmable Dividermentioning

confidence: 99%

A Low-voltage Programmable Frequency Divider with Wide Input Frequency Range

Liao

Fan

2018

ITM Web Conf.

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Abstract.A low-voltage programmable frequency divider with wide input frequency range is fabricated in standard 0.18µm TSMC RF CMOS technology and presented in this paper. Considering the frequency division ratio of dual-modulus prescaler is relatively smaller, a programmable divider with full custom design is used to increase the frequency division ratio and the maximum operating frequency. The frequency division ratio of the programmable frequency divider covers from 64 to 255. And the measured results show that the programmable divider works correctly when the input frequency varies from 0.5 GHz to 6.0 GHz, with 1V supply. Besides, the power consumption is 3.5 mA at the maximum frequency of 6.0 GHz.

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“…High operating frequencies, wide divide-ratio ranges, binary divide-ratio controls and 50% duty-cycle are the most common features of a highly efficient programmable frequency divider. A number of programmable dividers have been reported in the recent years [1,2,3,4,5], but none of them meet all the desired characteristics.…”

Section: Introductionmentioning

confidence: 99%

A fast programmable frequency divider with a wide dividing-ratio range and 50% duty-cycle

Zhang

Islam

Haider

2007

IEICE Electron. Express

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Abstract:A novel programmable frequency divider in 0.18-µm standard CMOS process is presented in this paper. With less cascode CMOS-stages, the proposed design achieves a higher operating frequency compared to that of the similar programmable frequency dividers reported in the literature. Test results demonstrate that the divider can operate up to 4.5 GHz. Elimination of passive resistors in the proposed scheme provides an area efficient design approach. Design improvements to achieve 50% duty cycle are also presented. Due to the lower operating frequency of the 50% duty cycle correction unit, it only adds a very small amount of power consumption penalty (∼ 10%) to the entire system. Keywords: programmable frequency divider, ring VCO, D latch, 50% duty-cycle Classification: Microwave and millimeter wave devices, circuits, and systems II, vol. 49, no. 9, pp. 638-642, Sept. 2002. [3] X. P. Yu, M. A. Do, L. Jia, J. G. Ma, and K. S. Yeo, "Design of a low power wide-band high resolution programmable frequency divider," IEEE Trans. References

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Design of a low power wide-band high resolution programmable frequency divider

Cited by 37 publications

References 8 publications

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4

A Low-voltage Programmable Frequency Divider with Wide Input Frequency Range

A fast programmable frequency divider with a wide dividing-ratio range and 50% duty-cycle

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