Design of a Low-Power Embedded System Based on a SoC-FPGA and the Honeybee Search Algorithm for Real-Time Video Tracking

Soubervielle‐Montalvo, Carlos; Perez-Cham, Oscar E.; Puente, Cesar; González-Galván, Emilio J.; Olague, Gustavo; Aguirre-Salado, Carlos Arturo; Cuevas-Tello, Juan C.; Ontañón-García, L. J.

doi:10.3390/s22031280

Cited by 6 publications

(3 citation statements)

References 64 publications

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“…9 The field-programmable gate array (FPGA) can be used as a proof-of-concept platform to validate methodologies and system architectures, monitor performance, integrate software, debug ports, analyze logic connections, and trace hardware. 10 FPGA physical interfaces include transistor-transistor logic input/output, universal serial bus, and ethernet to connect with other systems and extend platform features. FPGA platforms offer a high degree of reusability and optimize system architecture by manipulating buffers, bus bandwidths, and required code space volumes.…”

Section: Introductionmentioning

confidence: 99%

Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

Kumar,

Zhou,

Wang

et al. 2024

CNS Neurosci Ther

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AimsThe open‐loop nature of conventional deep brain stimulation (DBS) produces continuous and excessive stimulation to patients which contributes largely to increased prevalence of adverse side effects. Cerebellar ataxia is characterized by abnormal Purkinje cells (PCs) dendritic arborization, loss of PCs and motor coordination, and muscle weakness with no effective treatment. We aim to develop a real‐time field‐programmable gate array (FPGA) prototype targeting the deep cerebellar nuclei (DCN) to close the loop for ataxia using conditional double knockout mice with deletion of PC‐specific LIM homeobox (Lhx)1 and Lhx5, resulting in abnormal dendritic arborization and motor deficits.MethodsWe implanted multielectrode array in the DCN and muscles of ataxia mice. The beneficial effect of open‐loop DCN‐DBS or closed‐loop DCN‐DBS was compared by motor behavioral assessments, electromyography (EMG), and neural activities (neurospike and electroencephalogram) in freely moving mice. FPGA board, which performed complex real‐time computation, was used for closed‐loop DCN‐DBS system.ResultsClosed‐loop DCN‐DBS was triggered only when symptomatic muscle EMG was detected in a real‐time manner, which restored motor activities, electroencephalogram activities and neurospike properties completely in ataxia mice. Closed‐loop DCN‐DBS was more effective than an open‐loop paradigm as it reduced the frequency of DBS.ConclusionOur real‐time FPGA‐based DCN‐DBS system could be a potential clinical strategy for alleviating cerebellar ataxia and other movement disorders.

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Section: Introductionmentioning

confidence: 99%

Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

Kumar,

Zhou,

Wang

et al. 2024

CNS Neurosci Ther

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“…This approach provides a much shorter processing time compared to microcomputers or microcontrollers [21]. This FPGA technology-based approach provides fast, compact, low power consumption for computing and has the ability to execute multiple tasks in parallel [22], [23].…”

Section: Introductionmentioning

confidence: 99%

Implementation of first order statistical processor on FPGA for feature extraction

Hadiyoso,

Ramdani,

Irawati

et al. 2024

IJRES

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Statistical calculations on signals commonly used in feature extraction. In software processing, statistical computation is an easy task. However, providing a computer requires high costs for simple statistical processing. Another consideration is the need for implementation with real-time and portable processing. Therefore, an alternative device is needed, one of which is the field programmable gate array (FPGA). FPGA is a logic circuit board that can be reconfigured according to computing needs. FPGA can also be used as a prototyping of electronic chips. However, implementing statistical formulas in FPGA is interesting in developing its architecture. Therefore, this research proposes a logic circuit design that can be used for first-order statistical calculations. Statistical parameters include the mean, variance, standard deviation, skewness, and kurtosis. The validation test was performed on the electrocardiogram (ECG) signal series and compared with manual calculations. Validation shows that the mean and variance has very high accuracy with an average error of less than 0.06%.

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“…FPGAs are popular in low-power applications [16], because they consume two to three orders of magnitude less power than GPUs (depending on the device and implemented design). Rapuano provides a deep analysis in his article [17].…”

Section: Introductionmentioning

confidence: 99%

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA

Morcillo,

Báscones,

González

et al. 2024

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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k-means stands out as one of the most common clustering algorithms, widely employed for classification in hyperspectral imaging. In this context, large amounts of data are gathered by sensors that are embedded into satellites with strict constraints in terms of power consumption, weight, physical space or radiation tolerance. Since communication bandwidth is also limited, data processing must be performed on board. However, meeting all those constraints also entails a significant trade-off with computing performance. The aim of this work is clustering hyperspectral images in real-time. Custom hardware has been designed with the objective of reducing overhead and maximizing performance, by exploiting several acceleration techniques. The implementation targets a space-grade Xilinx Kintex FPGA, that features low power consumption and is shielded against radiation. The design has a deep pipelined architecture, able to process all bands of each hyperspectral pixel in parallel. In consequence, it attains a throughput of 100M hyperspectral pixels per second, even with a discrete use of FPGA resources. In addition, it is also fully parametric, with on-the-fly adaptation to different kinds of images and clustering configurations.Compared to previous implementations, ours takes advantage of a fully RTL design that avoids CPU bottlenecks and HLS design overheads. It also has a fixed throughput regardless of image or clustering properties, while having lower FPGA resource usage than performance-wise equivalent implementations.

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Design of a Low-Power Embedded System Based on a SoC-FPGA and the Honeybee Search Algorithm for Real-Time Video Tracking

Cited by 6 publications

References 64 publications

Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

Real‐time field‐programmable gate array‐based closed‐loop deep brain stimulation platform targeting cerebellar circuitry rescues motor deficits in a mouse model of cerebellar ataxia

Implementation of first order statistical processor on FPGA for feature extraction

Parametric Pipelined k-Means Implementation for Hyperspectral Processing on Spacecraft Embedded FPGA

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