Design of a Novel Envelope Detector for Fast-Settling Circuits

Alegre, J.P.; Celma, S.; Calvo, B.; Pozo, José

doi:10.1109/tim.2007.909618

Cited by 19 publications

(10 citation statements)

References 12 publications

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“…The second one starts the "tracking" during the second symbol, and "holding" and "discharging" during the third symbol. Thus, this technique employs one circuit to detect the peak of the odd symbols and the other circuit to detect that of the even symbols, in a similar way as the technique proposed in [8]. …”

Section: B Fine Gainmentioning

confidence: 99%

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

Alegre

Celma

Calvo

et al. 2009

IEEE Trans. Circuits Syst. II

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This brief presents a baseband automatic gain control (AGC) circuit for an IEEE 802.11a wireless local area network (WLAN) direct conversion receiver. The whole receiver is to be fully integrated in a low-cost 0.25-µm 75-GHz SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) process; thus, the AGC has been implemented in this technology by employing newly designed cells, such as a linear variable gain amplifier (VGA) and a fast-settling peak detector. Due to the stringent settling-time constraints of this system, a feedforward gain control architecture is proposed to achieve fast convergence. The proposed AGC is composed of two coarse-gain stages and a fine-gain stage, with a feedforward control loop for each stage. It converges with a gain error of below ±1 dB in less than 3.2 µs, whereas the power and area consumption are 13.75 mW and 0.225 mm 2 , respectively. IndexTerms-Bipolar complementary metal-oxidesemiconductor (BiCMOS) integrated circuits, feedforward systems, gain control, peak detector, variable gain amplifier (VGA), wireless local-area network (WLAN).

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Section: B Fine Gainmentioning

confidence: 99%

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

Alegre

Celma

Calvo

et al. 2009

IEEE Trans. Circuits Syst. II

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“…ASK demodulators can also be constructed using the envelope detector proposed by Alegre et al, as shown in Fig. 17 [22,23]. The current-mode precision full-wave rectifier is derived from the current squarer reported in [38,39] and formalized in a full-wave rectification form in [40].…”

Section: Mixed-mode Ask Demodulators For Passive Wireless Microsystemsmentioning

confidence: 99%

“…Fig. 17 Envelope detector by Alegre et al [22,23] Analog Integr Circ Sig Process (2010) 63: 33-45 41 To appreciate the elegance of the design, we need to understand the principle of the current squarer proposed by Bult and Wallinga [38] with its simplified schematic shown in Fig. 18(a).…”

Section: Mixed-mode Ask Demodulators For Passive Wireless Microsystemsmentioning

confidence: 99%

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Design techniques for ASK demodulators of passive wireless microsystems: a state-of-the-art review

Yuan

2009

Analog Integr Circ Sig Process

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ASK demodulators are widely used in passive wireless microsystems due to their simple design and low power consumption. Although a large number of ASK demodulators emerged recently, an in-depth examination of the pros and cons and design constraints of these ASK demodulators is not available. This paper presents a comprehensive in-depth review of the design techniques for ASK demodulators of passive wireless microsystems. The classification of ASK demodulators of passive wireless microsystems is introduced. We show that ASK demodulators of passive wireless microsystems can be classified into three categories on the basis of the information carriers: voltage-mode, current-mode, and mixed-mode. The design constraints of these ASK demodulators differ fundamentally. Challenges encountered in design of ASK modulators for passive wireless microsystems are examined in detail. The configurations of voltage-mode, currentmode and mixed-mode ASK demodulators for passive wireless microsystems emerged recently are studied and their circuit implementations are examined in detail. The performance of these ASK demodulators such as date rates, carrier frequencies, and modulation index is compared.

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“…[5] stresses the fast-setting detector but the operation frequency is low and the time-delay is still at the level of several milliseconds. [6] addresses the bandwidth of the detector, however, the circuit is complex.…”

Section: Introductionmentioning

confidence: 99%

A novel RF envelope detector with ultra-wide operation frequency range and enhanced transient response speed

Liu

Zhang

Chen

2017

IEICE Electron. Express

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This paper presents an envelope detector that can be used in an ultra-wide operation frequency range (1 GHz∼10 GHz) and the transient response time of the detector is less than several nanoseconds. The detector comprises an operational trans-conductance amplifier (OTA), a mirror and a buffer. An extra discharging path is added specially to accelerate the fallingdown transient process. The value of the discharging current and the choice of the charging/discharging capacitor are the key factors in the transient process. The circuit is implemented using HuaHong 0.18 µm standard CMOS technology. Simulation and measured results are offered showing both better frequency (up to 10 GHz) and transient (several nanoseconds of delay) performance.

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Design of a Novel Envelope Detector for Fast-Settling Circuits

Cited by 19 publications

References 12 publications

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

Design techniques for ASK demodulators of passive wireless microsystems: a state-of-the-art review

A novel RF envelope detector with ultra-wide operation frequency range and enhanced transient response speed

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