Design of a novel radix-4 booth multiplier

Lin, Hsin-Lei; Chang, Robert Chen-Hao; Chan, Ming-Tsai

doi:10.1109/apccas.2004.1413009

Cited by 11 publications

(1 citation statement)

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“…A thorough literature review depicts that the parallel multiplier lies in the critical path for delay measurement of its former system [5]. Also, the most significant part of the propagation latency in a parallel multiplier belongs to the Partial Product Reduction Tree (PPRT) consisting of the compressors [6]. As a consequence, delay reduction for PPRT in state-of-the-art schemes is one of the main concerns for the circuit designers.…”

Section: Introductionmentioning

confidence: 99%

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Rahnamaei

2020

Informacije MIDEM

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In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes.

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Section: Introductionmentioning

confidence: 99%