Design of a novel reversible multiplier circuit using modified full adder

Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates

“…Also it can produce two product terms simultaneously with two constant inputs. This feature of BVPPG gate reduces the number of reversible gates of the circuit compared to the designs of [12][13][14][15][16][17][18][19][20][21][22]. The figure 10 shows the partial product generator using new BVPPG gates.…”

“…This reduces the number of external fan-out gates to zero in our design which is main design feature. The proposed design is compared with the existing designs [11][12][13][14][15][16][17][18][19][20][21][22]. Table 1: Truth table of BVPPG gate Truth table INPUTS …”

“…In the existing literature on multiplier [13][14][15][16] operand bits are copied using 24 Feynman gates and in [14] the fan-out of input operands is achieved using 12 BVF gates. In [11] built-in fan-out using Toffoli gates and Peres gates is used .But in the proposed multiplier design duplication of the operands is achieved without using external fan-out gates.…”

“…Figure 13. Four operand addition circuit-MOA The existing 4*4 gates namely DPG [12], HNG [13], PFAG [14], MKG [15] and TSG [16], and can be individually used as an adder. It is shown that use of DPG gate [12] reduces the quantum cost of the multiplier to a minimum value.…”

“…There are different approaches of a multiplier design using reversible logic gates [11][12][13][14][15][16][17][18][19][20][21][22]. The proposed multiplier uses parallel multiplier consists of two steps.…”