Design of a one-megacycle iteration rate DDA

Bradley, Robert E.; Genna, J. F.

doi:10.1145/1460833.1460874

Cited by 14 publications

(3 citation statements)

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“…Although the DDA was initially unable to match the speed of analog computers, advances in design quickly reduced the performance gap. TRICE [21 J was produced in 1958, with parallel configuration of integrators giving an increase in speed of three orders of magnitude over previous DDAs, then a further order of magnitude improvement was achieved by the introduction of parallel-serial arithmetic by Bradley and Genna [22], who achieved an iteration rate of one megacycle in 1962.…”

Section: A Short History Of Ddasmentioning

confidence: 99%

10 Digital differential analysers

Shileiko¹

2022

Analog Computing

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To avoid the initialisation procedures, analog computers are now rarely used unless interfaced to general purpose digital hardware in a hybrid configuration, whi eh implementation due to the need for matrix inversion.Australia [14,15], and Czechoslovakia [16,17], suggesting that the DDA still retains the interest of a significant number of research establishments. Aims and Contributions of this ThesisThe three principle aims of the research described in the following Chapters are: 1. to investigate the feasibility of incorporating automatically varying step-size into DDA integration; 2. to analyse DDA suppression of truncation error during solution of nonlinear equations ; 3. to introduce a new stiff integration technique, based on existing explicit integration methods and suitable for DDA hardware implementation. A result of this research has been the discovery of a new class of DEs, which has proved to be particularly useful in the testing of VSS integration algorithms. These new equations have been combined with a selection from the literature to produce a comprehensive set of DEs for testing VSS DDA integration.Thus original contributions are considered to have been made in a total of four separate areas within the DDA field.

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Section: A Short History Of Ddasmentioning

confidence: 99%

10 Digital differential analysers

Shileiko¹

2022

Analog Computing

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“…Center in the SPEDAC computer (9). Each of these machines used a separate arithmetic unit and storage in the form of a delay In all incremental machines developed to date using a time-shared arithmetic unit, a common iteration frequency has been used for all integrators and this frequency has been limited to from 50 ops to 400 cps by hardware limitations.…”

Section: A Past Applications Of Incremental Processorsmentioning

confidence: 99%

An investigation of a multiple iteration rate incremental data processor

Bruce

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“…digital differential analyzers through 1956 has been collected and an extensive treatise published by Forbes (5). (8). At present, high speed digital differential analyzers exist with digital computer accuracy although they are not widely used because of the Investment required for such a special purpose machine.…”

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A digital differential analyzer programming system for the IBM 7074 computer

Farris

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Design of a one-megacycle iteration rate DDA

Cited by 14 publications

References 1 publication

10 Digital differential analysers

10 Digital differential analysers

An investigation of a multiple iteration rate incremental data processor

A digital differential analyzer programming system for the IBM 7074 computer

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