Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate

Kan, Tsang-Chi; Yang, Shih-Hsien; Chang, Ting-Feng; Ruan, Shanq-Jang

doi:10.1109/tvlsi.2011.2176968

Cited by 4 publications

(6 citation statements)

References 9 publications

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“…1 (b), the rectangle-via can be used for redundant via insertion in 65nm or beyond processes. Note that characterization of vias depends on offerings of foundries [10]. As illustrated in [10], this discussion also assurnes the (2) where Ev and Erv denote the enclosure of via and rectangIe via; SV1 and RV1 represent the length of via and rectangIe via; Sv-v is the minimum spacing between two vias, respectively.…”

Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 91%

“…Note that characterization of vias depends on offerings of foundries [10]. As illustrated in [10], this discussion also assurnes the (2) where Ev and Erv denote the enclosure of via and rectangIe via; SV1 and RV1 represent the length of via and rectangIe via; Sv-v is the minimum spacing between two vias, respectively. Note that different foundries have their own design rules, especially the dimensions of via enclosure and spacing within metals may be different as shown in Figs.…”

Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 91%

“…For a given design, the accessibility of standard cells pins not only determine the design routability but also account for the insertion rate of redundant vias for routers [10], [11]. The resources of metal I pins of a standard cell determine the accessibility of pins, for redundant vial insertion.…”

Section: Preliminariesmentioning

confidence: 99%

“…Although standard cell libraries can be effectively enhanced to increase redundant vial insertion rate [9], [10], the cell height constrains the redundant via insertion and the use of expandable metalipins, especially for a limited height SC library. Therefore, the limitation on the area of the conventional SC design motivates the present of an effective redundant via-aware SC design that uses an automatie redundant via checking and optimizing schemes for SC library.…”

Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 99%

“…Our proposed method, Enhanced Redundant Via Library Checker and Optimizer (ERVLCO), includes two parts: an Enhanced Redundant Via Library Checker (ERVLC) and a Geometry-Based Layout Optimizer (GBLO), which are adopted to perform the efficient checking and optimization of all metal 1 pins in a library. Note that, the characterization of a standard cell does not change in input capacitance and cell delay (typically less than 0.1% [10]) during optimization. Finally, implementations of the method in practical industrial applications demonstrate the effectiveness of the double-via and rectangle-via insertion.…”

Section: Geometry and Area Of Redundant Viasmentioning

confidence: 99%

See 4 more Smart Citations

Configurable redundant via-aware standard cell design considering multi-via mechanism

Kan

Hong

Chen

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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�ell designed redundant via-aware standard ceHs (SCs) can mcrease the redundant vial insertion rate in ceH-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low vial insertion rate in nanometer regimes, but also demonstrates an efficient automatie layout optimizer for designing standard ceHs. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant vial insertion rate by a total of 26.3%. KeywordsDesign for manufacturability (DFM), layout, redundant via, standard ceH (SC)

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Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 91%

Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 91%

Section: Preliminariesmentioning

confidence: 99%

Section: B Standard Cell Design and Layout Limitationmentioning

confidence: 99%

Section: Geometry and Area Of Redundant Viasmentioning

confidence: 99%

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Configurable redundant via-aware standard cell design considering multi-via mechanism

Kan

Hong

Chen

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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A method for timing constrained redundant via insertion

Wang

2014

J. Semicond.

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Redundant via (RV) insertion is a useful mechanism to enhance via reliability. However, when extra vias are inserted into the design, the circuit timing might be changed. Therefore, how to insert RV under the timing constraints is the main challenge. In this paper, we introduce a new model to compute the distance between a RV and the corresponding single via, put forward a new RV type, which is called the long length via (LLV), and then present an improved RV insertion method considering the timing constraints. This computing model can certify that the timing, which is obtained after inserting a RV, is not greater than the original timing. Meanwhile, the new RV type LLV can increase the possibility of RV insertion; this method provides a global perspective for the RV insertion. Considering the timing constraints, the total redundant via insertion rate is 85.38% in the MIS-based method, while our proposed method can obtain a high insertion rate 88.79% for the tested circuits.

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Redundant Via Insertion Based on SCA

Wang

Xing

et al. 2016

IEEE Trans. VLSI Syst.

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Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate

Cited by 4 publications

References 9 publications

Configurable redundant via-aware standard cell design considering multi-via mechanism

Configurable redundant via-aware standard cell design considering multi-via mechanism

A method for timing constrained redundant via insertion

Redundant Via Insertion Based on SCA

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