Design of a reconfigurable AES encryption/decryption engine for mobile terminals

Pionteck, Thilo; Staake, Thorsten; Stiefmeier, Thomas; Kabulepa, Lukusa D.; Glesner, Manfred

doi:10.1109/iscas.2004.1329329

Cited by 22 publications

(12 citation statements)

References 5 publications

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“…Pionteck et al [69] present a dynamically reconfigurable function-unit for error detection and correction in mobile terminals. The same authors have presented a reconfigurable encryption engine for mobile terminals [68]. Creates a basic frame by copying data from a source location to the packetmemory, and appends a header to it.…”

Section: Sequence Of Functionsmentioning

confidence: 99%

“…The similarity of different algorithms may be used to incorporate units (inside this RFU or as a separate RFU) that best exploit this similarity. As an example, Logger et al [51] propose a reconfigurable encryption unit that can implement three different encryption algorithms; RC4, DES and 3DES, while Pionteck et al [68] [69,70].…”

Section: Crypto-rfumentioning

confidence: 99%

“…Hamalainen et al [27] gives figures for RC4 implementation using 255 CLBs of a Xilinx XC4000 device, which is 7.3K equivalent ASIC gates. Pionteck et al [68] discuss the implementation of a reconfigurable AES implementation, and the complete Hardware/Software partitioned implementation took 1.374mm 2 on a 0.25um technology, which approximates to 34K gates. From [95], it can be seen that a 3DES implementation uses 125% of an AES implementation.…”

Section: Drmp Estimatesmentioning

confidence: 99%

“…Pionteck et al [68] mention a reconfigurable AES encryption module in which area overheads of reconfiguration logic and tables is 6.5%. For DRMP , the approximation is a 7% overhead of reconfiguration, in terms of both area and gate usage.…”

Section: Drmp Estimatesmentioning

confidence: 99%

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A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

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Nabi, Syed Waqar (2009) A coarse-grained dynamically reconfigurable MAC processor for power-sensitive multi-standard devices. EngD thesis.http://theses.gla.ac.uk/865/ Copyright and moral rights for this thesis are retained by the author A copy can be downloaded for personal non-commercial research or study, without prior permission or charge This thesis cannot be reproduced or quoted extensively from without first obtaining permission in writing from the Author The content must not be changed in any way or sold commercially in any format or medium without the formal permission of the Author When referring to this work, full bibliographic details including the author, title, awarding institution and date of the thesis must be given Copyright c Syed Waqar Nabi October 2008In the name of Allah, the Beneficent, the Merciful.Read: In the name of thy Lord Who createth, Createth man from a clot. Read: And thy Lord is the Most Bounteous, Who teacheth by the pen, Teacheth man that which he knew not. Nay, but verily man is rebellious That he thinketh himself independent! Lo! unto thy Lord is the return.The Quran; Chapter 96, Verses 1-7 i Abstract DRMP, a Dynamically Reconfigurable MAC Processor, is an innovative, dynamically reconfigurable System-on-Chip architecture. The architecture exploits substantial overlaps in the functionality of different wireless MAC layers. Its flexibility is specialized for addressing the requirements of the MAC layer of wireless standards. It is targeted at consumer, multi-standard, handheld devices, and its design is meant to address the balance of flexibility and power-efficiency that this target market demands. The DRMP reconfigures packet-by-packet on the fly, allowing execution of concurrent protocol modes on a single hardware co-processor. An interrupt-driven programming model has also been presented and shown to implement the protocol state-machine of the three protocols on a CPU. These features will allow the DRMP to replace three MAC processors in a hand-held device. The most innovative component of the DRMP architecture is its Interface and Reconfiguration Controller. It uses a combination of asynchronous controllers to dynamically reconfigure the functional units in the architecture and delegate MAC tasks to them. The architecture has been modeled in Simulink at cycle-approximate abstraction. Results of simulations involving transmission and reception of packets have been presented, showing that the platform concurrently handles three protocol streams, reconfigures dynamically, yet meets and exceeds the protocol timing constraints, all at a moderate frequency. Its heterogeneous and coarse-grained functional units, limited connectivity requirements between these units, and proportionally large time that these resources are idle, promise a very modest power-consumption, suitable for mobile devices, while offering flexibility to implement different MAC protocols. The Institute of System Level Integration in general, the EngD center and Sian Williams in particular, deserve a special t...

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Section: Sequence Of Functionsmentioning

confidence: 99%

Section: Crypto-rfumentioning

confidence: 99%

Section: Drmp Estimatesmentioning

confidence: 99%

Section: Drmp Estimatesmentioning

confidence: 99%

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A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

Nabi

Wells

Vanderbauwhede

2008

2008 IEEE International SOC Conference

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“…In general, stream ciphers have lower complexity and higher throughput than block ciphers. Due to these attractive properties, stream ciphers are widely used in embedded/mobile applications such GSM telephony (the A5 family of stream ciphers [3]), the 802. 11 Wireless Encryption Protocol (WEP) [4] and Secure Sockets Layer (SSL) [5]-both use the RC4 stream cipher and the Bluetooth protocol (E0 stream cipher) [6].…”

Section: Introductionmentioning

confidence: 99%

On Parallelizing the CryptMT Stream Cipher

Stefan

Nummey

Harwayne-Gidansky

et al. 2008

VTC Spring 2008 - IEEE Vehicular Technology Conference

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Abstract-Fast stream ciphers are used extensively for encrypted data transmission in mobile networks and over multigigabit links. CryptMT, a recently proposed stream cipher, is one of the final candidates for standardization by the European Union's eSTREAM project. Cryptanalysis of CryptMT has discovered no feasible attacks thus far.We present a scalable technique for parallelizing CryptMT and present an area-efficient hardware implementation on a fieldprogrammable gate array (FPGA). On the Xilinx Virtex-2 Pro FPGA, a 2× parallelization delivers throughputs of up to 16 Gbits/s while using minimal logic resources (1,782 slices). This is highly area-efficient compared to implementations of ciphers such as AES. Possibilities for higher degrees of parallelization are also discussed.

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On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction

Pionteck

Stiefmeier

Staake

et al.

Vlsi-Soc: From Systems to Silicon

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This paper presents the design of a function-specific dynamically reconfigurable architecture for error detection and error correction. The function-unit is integrated in a pipelined 32 bit RISC processor and provides full hardware support for encoding and decoding of Reed-Solomon Codes with different code lengths as well as error detection methods like bit-parallel Cyclic Redundancy Check codes computation. The architecture is designed and optimized for the usage in the medium access control layer of mobile wireless communication systems and provides simultaneously hardware support for control-flow and data-flow oriented tasks.

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Design of a reconfigurable AES encryption/decryption engine for mobile terminals

Cited by 22 publications

References 5 publications

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices

On Parallelizing the CryptMT Stream Cipher

On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction

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