Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS

Xavier, J. A. R.; Barquinha, Pedro; Goes, J.

doi:10.1109/dcis53048.2021.9666185

2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS) 2021

DOI: 10.1109/dcis53048.2021.9666185

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Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS

J. A. R. Xavier

Pedro Barquinha

J. Goes

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2024

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Cited by 2 publications

References 16 publications

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A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

Yamashita,

Hershberg,

Yoshioka

et al. 2024

IEEE J. Solid-State Circuits

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A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

Yamashita,

Hershberg,

Yoshioka

et al. 2024

IEEE J. Solid-State Circuits

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A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

Lim,

Lee,

Lee

et al. 2024

IEEE J. Solid-State Circuits

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Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS

Cited by 2 publications

References 16 publications

A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

A 4.6–400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

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