Design of a Robust Analog-to-Digital Converter Based on Complementary SET/CMOS Hybrid Amplifier

Improved hybrid SET/MOS Digital-Analog and Analog-Digital Converters

“…13 shows the circuit diagram for a SET inverter. To simulate a SET inverter with 50% duty ratio, V G has been adjusted to V G1 =0V and V G2 =-0.16V [22]. When the upper SET turns on, the lower SET turns off because SET has the inherent Coulomb oscillation characteristics with the period of q/C g [22].…”

“…To simulate a SET inverter with 50% duty ratio, V G has been adjusted to V G1 =0V and V G2 =-0.16V [22]. When the upper SET turns on, the lower SET turns off because SET has the inherent Coulomb oscillation characteristics with the period of q/C g [22]. The circuit parameters are as follows: The supply voltage V DD =10mV, C G1 =0.24E-18, C G2 =0, the capacitances of tunnel junctions C 1 =C 2 =1.3E-18, the resistances of tunnel junctions R 1 =R 2 =1.3E6, T=30K and the load capacitance C L = 1pF [22].…”

A Low Power Flash ADC using Single-Electron Transistor

“…Rathnakannanet al [7] proposed three methods of Analog to Digital Conversion techniques for Eight-bit operation using Complementary Single Electron Tunneling Transistor, Periodic Symmetric Function, SET/MOS hybrid using Single ElectronTransistor. Choong Hyun Leeet al [8] proposed Complementary single-electron transistor (SET)/CMOS hybrid amplifier based analog-to-digital converter with the combination of the amplification of SET current by MOSFETs and also suppress the Coulomb blockade oscillation current by increasing the island size, gate bias voltage and temperature.The conversion speed of ADC depends on the performance ofthe sample and hold block which could be improved by Hybrid SET a combination of SET and MOSFET, but the drawback is more power consumption [8]. Flash ADC requires a large number of comparatorscompared to other ADCs [9].…”