Design of a scalable network programming framework

Wun, Ben; Crowley, Patrick; Raghunath, Arun

doi:10.1145/1477942.1477945

“…Shangri-la [8] follows a more general approach and consists in a domain-specific programming language named Baker and a profile-guided compiler infrastructure, which is able to optimize and map an application onto Intel IXP NPUs. The Network Runtime Environment (NRTE) [32] is a runtime system implemented as a C library, aiming at providing a network programming environment for multicore NPUs. The programmer is in charge of defining a set of thread-safe packet processing functions that the runtime environment will map onto the underlying platform, possibly replicating some of them across the available hardware threads.…”

Section: Related Workmentioning

confidence: 99%

“…Having work units flow in a way that is similar to what is specified by the dataflow model is not a novelty in networking applications [8,21,25,32], as these applications can be effectively described as a collection of relatively independent packet-processing tasks. In our case, the data-driven processing model allows a seamless migration of jobs between one processing element to the following, while sequentiality avoiding the usage of synchronization primitives in the code.…”

Section: The Netvm Processing Model: Sequentiality Modularity and Dmentioning

confidence: 99%

Creating portable and efficient packet processing applications

Morandi

¹

,

Risso

²

,

Rolando

³

et al. 2011

Des Autom Embed Syst

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Network processors are special-purpose programmable units deployed in many modern high-speed network devices, which combine flexibility and high performance. However, software development for these platforms is traditionally cumbersome due both to the lack of adequate programming abstractions and to the impossibility of reusing the same software on different hardware platforms.In this context, the Network Virtual Machine (NetVM) aims at defining an abstraction layer for the development of portable and efficient data-plane packet processing applications. Portability and efficiency are achieved altogether by virtualizing the hardware and by capturing in the programming model the peculiar characteristics of the application domain.This paper validates the NetVM model, demonstrating that the proposed abstraction coupled with a proper implementation of the NetVM Framework is able to provide generality (i.e., capability to support a wide range of applications), software portability across heterogeneous network processor architectures, and efficiency of the generated code, often exceeding the one obtained using state-of-the-art compilers.

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“…Network processors have not enjoyed the smooth, continual evolution of microprocessors, with new versions of a given processor often requiring rewriting substantial portions of the code. (Wun et al present an approach toward unifying the programming interface in [43]). They also remain difficult to program for high-level analysis due to their lack of the powerful cached memory semantics of a commodity microprocessor.…”

Section: Related Workmentioning

confidence: 99%

An architecture for exploiting multi-core processors to parallelize network intrusion prevention

Paxson

¹

,

Sommer

²

,

Weaver³

2007

2007 IEEE Sarnoff Symposium

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SUMMARYIt is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of the rising sophistication of attacks requiring more complex analyses to detect; the relentless growth in the volume of network traffic that we must analyze; and, critically, the failure in recent years for uniprocessor performance to sustain the exponential gains that for so many years CPUs have enjoyed. For commodity hardware, tomorrow's performance gains will instead come from multi-core architectures in which a whole set of CPUs executes concurrently. Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach. In this work we frame an architecture customized for parallel execution of network attack analysis. At the lowest layer of the architecture is an 'Active Network Interface', a custom device based on an inexpensive FPGA platform. The analysis itself is structured as an event-based system, which allows us to find many opportunities for concurrent execution, since events introduce a natural asynchrony into the analysis while still maintaining good cache locality. A preliminary evaluation demonstrates the potential of this architecture. Copyright

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An architecture for exploiting multi‐core processors to parallelize network intrusion prevention

Sommer

¹

,

Paxson

²

,

Weaver

³

2009

Concurrency and Computation

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SUMMARYIt is becoming increasingly difficult to implement effective systems for preventing network attacks, due to the combination of the rising sophistication of attacks requiring more complex analyses to detect; the relentless growth in the volume of network traffic that we must analyze; and, critically, the failure in recent years for uniprocessor performance to sustain the exponential gains that for so many years CPUs have enjoyed. For commodity hardware, tomorrow's performance gains will instead come from multi-core architectures in which a whole set of CPUs executes concurrently. Taking advantage of the full power of multi-core processors for network intrusion prevention requires an in-depth approach. In this work we frame an architecture customized for parallel execution of network attack analysis. At the lowest layer of the architecture is an 'Active Network Interface', a custom device based on an inexpensive FPGA platform. The analysis itself is structured as an event-based system, which allows us to find many opportunities for concurrent execution, since events introduce a natural asynchrony into the analysis while still maintaining good cache locality. A preliminary evaluation demonstrates the potential of this architecture. Copyright

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Design of a scalable network programming framework

Cited by 7 publications

References 11 publications

Creating portable and efficient packet processing applications

Creating portable and efficient packet processing applications

An architecture for exploiting multi-core processors to parallelize network intrusion prevention

An architecture for exploiting multi‐core processors to parallelize network intrusion prevention

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