Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips

Abstract

Absfract-This paper presents a memory architecture with the capability of self-testing and self-repairing. The contributions of this memory architecture are twofold. Firstly, it incorporates selftesting and self-repairing structures in the memory. As a result, the memory chips can perform tests, locate faults, and repair itself without any external assistance from either test engineers or test equipment, This will drastically improve the functional yield and reduce the production cost, Secondly, the proposed memory architecture uses a hierarchical organization to achieve optimal conditions for memory access time. The hierarchical organization also helps increase the efficiency of the self-testing and self-repairing structures.

A physical design tool for built-in self-repairable static RAMs

“…The BISR area overheads are found to be comparable with results published by other researchers [10]. Most researchers base their results on either a custom layout for a specific process technology or a very rough transistor count metric.…”

A physical design tool for built-in self-repairable RAMs

“…Even if we count the redundant rows as overhead, the fact that we have only 4 redundant rows in the array containing 512 or 1024 regular rows (see Table I), causes their contribution to be much less than 1% of the RAM array area without redundant rows. The BISR area overheads are found to be comparable with results published by other researchers, such as [5]. Most researchers base their results on either a custom layout or a very rough transistor count metric, and typically for one specific process technology.…”

“…This scheme was originally designed to repair single address location faults, because only one faulty address location could be registered. Chen and Sunada [5] have extended this design to repair multiple faults and have also proposed a novel architecture to reduce the access time penalty, one of the main drawbacks of the address comparison method. Hence their architecture is suitable for high-capacity SRAMs.…”

“…Chen and Sunada [5] have used a hierarchical cell array organization to minimize the overall memory access time. Two salient features of their design are: having the self-test and selfrepair logic away from the critical data path to minimize delays and keeping the self-repair logic as simple as possible to minimize sensitivity to processing defects.…”

Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits

“…Compared to logic circuits, SRAM cells are generally sized minimally and are more prone to noise effects. However, high-level error correction or self-repair techniques, such as error correction code [29] or redundant columns and rows [10], may be adopted to relax the constraints on PNMV. …”