Design of a SystemVerilog-Based VCO Real Number Model

Georgoulopoulos, Nikolaos; Mekras, Athanasios; Hatzopoulos, A.A.

doi:10.1109/mocast.2019.8741782

Cited by 2 publications

(1 citation statement)

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“…The maximum controlled voltage gives the maximum frequency and above this voltage, the frequency is saturated at the maximum frequency. The minimum controlled voltage gives the minimum frequency and below this voltage, the frequency is saturated at the minimum frequency [28], [29]. The tuning range is dedicated to the needed frequency range of the application and the variation of the required oscillation frequency due to process and temperature.…”

Section: Voltage Controlled Oscillator (Vco)mentioning

confidence: 99%

Increasing the Modeling Accuracy of an Analog PLL Device Executed With an Event-Driven Simulator

Maurice,

Dessouky,

Salem

2023

IEEE Access

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Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it's one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first-order Low Pass Filter (LPF). The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by the User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the Multi-stAge noiSe sHaping (MASH) 1-1-1 topology to generate the fractional part. Modelling non-linear effect like the phase noise of each sub-block, which is converted to the Root Mean Square (RMS)-jitter, by using the 'class' datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, taking the loading effect due to capacitances and resistances at the output by using the User-Defined Resolved Nets (UDRN). The simulation results ensure that there is an accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used.INDEX TERMS Real number modeling (RNM), SystemVerilog (SV), user-defined types (UDT), userdefined resolved nets (UDRN), phase locked loops (PLL), fractional dividers, piece-wise linear (PWL), phase noise (PN), RMS jitter, hardware description and verification language (HDVL).

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Section: Voltage Controlled Oscillator (Vco)mentioning

confidence: 99%