Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation

Abstract

This paper presents a well-established low power sample & hold circuitry, implemented in 180-nm CMOS technology. This circuit uses a systematic and optimal design of hybrid cascode compensation method which is used in fully differential two-stage CMOS operational transconductance amplifiers (OTAs). The circuit achieves minimum SNR of 74dB in all corner cases. Also average current dissipation of the whole circuit is measured to be 7.1mA in Typical-Typical corner case. SNR and total current dissipation of the circuit is calculated and listed in different corner cases. Although the sample and hold circuit meets the requirements of SNR specifications, this success does not seem to be outstanding. However, small amount of current dissipation which comes from the low-power OTA configuration is a great success.