Design of a wideband delay element for transmitted reference UWB receivers

Abstract

The transmitted reference ultra-wideband (TR-UWB) scheme has generated considerable interest in the field of UWB radio and on-chip wireless interconnect systems. This paper presents a wideband delay element (WBDE) which is a major design concern for TR-UWB transceivers and introduces a novel WBDE architecture that eliminates the need for dual bipolar power supplies. A very wide range of delays of monotonic nature (100-1000ps) can be achieved by varying the dimensions of the transistors, the power supply voltage, the shunt capacitances and the number of stages in the delay chain. The WBDE, designed using IBM® 90nm CMOS technology, would make the circuit implementation of TR-UWB schemes realizable.

A passive-matched 22 GHz 2.6-dB-NF CMOS front-end with a 70-800 ps delay block

“…The proposed architecture of a divided wideband delay-block (DB) built with 90 nm transistors and capable of processing bipolar message carrying pulses [22] is presented in Fig. 3.…”

“…9(b) presents its delayed versions collected from the output ports of the proposed multi-stage delay-block. In addition to the number of stages in a DB section, tuning of delay may also be controlled by shunt capacitors, ratio of transistors, and magnitude of rail voltage [22]. This phenomenon is further illustrated in tabular form for a single-stage delay-block in the following section.…”

“…R add.3 and R add.4 form a second resistive summer which combines the sectional responses to generate a complete delayed pulse train at node z with relatively small signal dispersion. The overall delay achieved by the proposed single-stage DB is not fixated at 180 ps but can be fine tuned with a number of design parameters[22], as will be explained in the following sections.The branched architecture of the delay-block allows extension of number of stages in each section (up to eight) during the testing process.Fig. 4presents a four-stage wideband delay-block where eight delay units (stage top.1-4 and stage bot.1-4 ) are divided between two sections/branches of the…”

High-Gain Power-Efficient Front- and Back-End Designs for a 90 nm Transmit-Reference Receiver

“…The amplifier output (RF signal) and its delayed version (LO signal), produced by a specially designed delay unit (DU), are subjected as excitations to an RF mixer or correlator. This feature of self-synchronization reduces the receiver's architectural complexity but introduces the challenge of designing analog delay lines to align the LO signal with the amplifier output [8]. At the end of the front-end, the RF mixer facilitates the process of decoding the input data form the pulse stream.…”

A window detection technique with adjustable threshold for transmitted reference receivers

“…The two inputs of the RF mixer consist of the output generated by the LNA and the output from an integrated delay element (DE). This customized delay element can be implemented using a branched architecture of cascaded inverters combined with resistive adders to delay the bipolar portions of the UWB pulses [8]. The objective of the DE is to produce the second input to the mixer from the received and processed RF signal.…”