Design of ADPLL system for WiMAX applications in 40-nm CMOS

Jiang, Wenlong; Tavakol, A.; Effendrik, Popong; Gevel, M. van de; Verwaal, F.; Staszewski, Robert Bogdan

doi:10.1109/icecs.2012.6463568

Cited by 6 publications

(3 citation statements)

References 4 publications

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“…Their target dual-band ADPLL is designed to use the concurrent division of a single DCO output. Figure 6 shows a simplified internal circuit, which was presented in [7,8].…”

Section: Proposed Dbdco and Wbdcomentioning

confidence: 99%

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Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Souri

Ghaznavi‐Ghoushchi

2015

Circuits Syst Signal Process

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Digitally controlled oscillators are the main cores in all-digital phase-locked loops (ADPLL), which are important for determining the range of frequency and power consumption in ADPLLs. In the conventional digitally controlled oscillator (DCO) designs, one single band of operation is assigned to the DCO. The following paper presents a new approach in the design of DCOs, which works in dual-band and wide-band modes with a control unit. In dual-band mode, the DCO works in two different ranges of frequencies simultaneously via digital control bits. The wide-band DCO (WBDCO) works in one wider range of frequencies consecutively. It seems that in the wide-band DCO, the gap width for the dual-band DCO (DBDCO) is zero. The previously mentioned designs allow the designer to have standard frequencies with the help of direct or multiplied frequencies. So, we can have a trade-off between power and performance. This means that we can have low power consumption in low-frequency applications and vice versa. The proposed designs are based on using digitally controlled capacitors, current starving gates and Schmitt triggers in critical points of the DCO loop, while preserving coarse and fine tunings. The non-delay linearity factors are clearly investigated and resolved with the use of a new combined control unit. The simulations of the proposed designs are performed in Hspice with a voltage of VDD = 1.8 v in 180 nm CMOS technology for 64-and 128-bit input coarse codes. Our simulation and evaluation results showed that in the dual-band DCO, a 14.8 ps jitter was calculated at 134 MHz with 1.2131 mW power consumption, while in the wide band with overlap mode, a 68.7 ps jitter was measured at 184.61 MHz

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“…Their target dual-band ADPLL is designed to use the concurrent division of a single DCO output. Figure 6 shows a simplified internal circuit, which was presented in [7,8].…”

Section: Proposed Dbdco and Wbdcomentioning

confidence: 99%

“…DCO and dividers used in dual-band ADPLL[7,8] The conceptual model definition on a dual-band and b wide-band…”

mentioning

confidence: 99%

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Souri

Ghaznavi‐Ghoushchi

2015

Circuits Syst Signal Process

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show abstract

“…Literature Survey [1][2][3][4][5][6][7][8][9][10] reveals that ADPLL outperforms classical PLLs and have more significance towards communication systems as well as consumer applications. However, exploring in depth it can be found that there are numerous real-time application environments such as space radiation conditions where ADPLL undergoes adversaries due to emergence of relatively small square impulse in the main signal.…”

Section: Introductionmentioning

confidence: 99%

A Robust and Efficient Fault-Resilient Rad Hard ADPLL

Prasad*,

Sandya

2019

IJEAT

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Typically, classical PLLs adopt analog design methods. However integrating PLL with noise-prone application environment is highly tedious and somewhere confined. As per current knowledge majority of PLLs apply Analog Loop Filters (ALFs) and Voltage Controlled Oscillators which are practically highly complicated to integrate with noisy environment. Even the traditional PLLs can’t be ported to the advanced processors. In last few years, the emergence of deep-submicron CMOS technologies have enabled digitization of major traditional analog circuits, comprising the analog PLLs that as a result could be vital to overcome above mentioned issues and to achieve more efficient solution than classical analog implementation

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A 2.57GHz All-Digital Phase-Locked Loop Based on the digital controlled Ring Oscillator

Ruan

Wang

2019

2019 11th International Conference on Information Technology and Electrical Engineering (ICITEE)

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Design of ADPLL system for WiMAX applications in 40-nm CMOS

Cited by 6 publications

References 4 publications

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

Two Efficient Dual-Band and Wide-Band Low-Power DCO Designs Using Current Starving Gates, DCV and Reconfigurable Schmitt Triggers in 180 nm

A Robust and Efficient Fault-Resilient Rad Hard ADPLL

A 2.57GHz All-Digital Phase-Locked Loop Based on the digital controlled Ring Oscillator

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