Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA

Parane, Khyamling; Prasad, B. M. Prabhu; Talawar, Basavaraj

doi:10.1109/vlsi-dat.2019.8741845

Cited by 5 publications

(2 citation statements)

References 7 publications

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“…In reconfigurable arrays, effective data interaction among processing elements relies on a routing network formed by interconnecting electrical and optical routers. Parane et al proposed an adaptive, cost-effective router structure that ensures high reliability under congestion by influencing crossbars, routing algorithms, and router pipeline optimization [10]. Nevertheless, the use of cache bypasses and multiplexers increases hardware overhead and power consumption.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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Addressing challenges regarding Hybrid Optoelectronic Network-on-Chip systems, such as congestion control, their limited adaptability, and their inability to facilitate optoelectronic co-simulation, this study introduces an adaptive hybrid optoelectronic interconnection shunt structure tailored for reconfigurable array processors. Within this framework, an adaptive shunt routing algorithm and a low-loss non-blocking five-port optical router are developed. Furthermore, an adaptive hybrid optoelectronic interconnection simulation model and a performance statistical model, established using SystemVerilog and Verilog, complement these designs. The experimental results showcase promising enhancements: the designed routing algorithm demonstrates an average 17.5% improvement in mitigating congestion at network edge nodes; substantial reductions in the required number of cross waveguides and micro-ring resonators for optical routers lead to an average path insertion loss of only 0.522 dB. Moreover, the hybrid optoelectronic interconnection performance statistical model supports the design of routing strategies and topology structures, enabling resource usage, power consumption, insertion loss, and other performance metrics to be accurately assessed.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Yang,

Li,

et al. 2024

Electronics

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“…Local and global computer networks are the basis of the communication infrastructure of modern society. Due to the growth of networks, the problem of choosing the optimal network equipment (routers, switches) is becoming more and more acute [1]. The central element of the information network is the router.…”

Section: Introductionmentioning

confidence: 99%

A Cost-Efficient Software Based Router and Traffic Generator for Simulation and Testing of IP Network

Przystupa

Beshley

et al. 2019

Electronics

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The development was carried out using the Qt5.2 integrated development environment, which uses the programming language C++. The main advantage of this environment is that the code written in it can be compiled to different platforms (for example, Windows, Linux, Mac OS). A software router based on a modular architecture has been developed. It uses the socket technology, which allows forming a program-oriented packet network with any topology, including full-coupled topology. A network traffic generator to test the developed software router has been designed. We proposed a scheme to measure the packet processing time of a router using a specialized packet-capture network interface cards (NIC 1 and NIC 2) and a novel traffic generator installed on PC. Based on an experimental test bed we confirmed that our software router provides a cost-efficient alternative to the expensive, special hardware router CISCO 2801.

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A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

2023

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R. PARRA-MICHEL was born in Guadalajara, Mexico, in 1973. He received the B.Sc. degree in electronics and communications from the University of Guadalajara, in 1996, the M.Sc. degree in electrical engineering specializing in communications from CINVESTAV-IPN, Guadalajara, in 1998, and the Ph.D. degree in electrical engineering specialized in digital signal processing for communications from CINVESTAV-IPN, Mexico City, in 2003. He has collaborated with several companies and institutions either in academic or technology projects, such as Siemens, Lucent, Mabe, Mixbaal, Hewlett-Packard, and Intel. He is currently the Director of Guadalajara Unit, CINVESTAV-IPN, and the Head of the Wireless Communication Group. His research interests include modeling, simulation, estimation and equalization of communication channels, digital implementation of DSP algorithms for communication systems and on-chip networks.

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Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA

Cited by 5 publications

References 7 publications

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

Design and Implementation of Reconfigurable Array Adaptive Optoelectronic Hybrid Interconnect Shunting Network

A Cost-Efficient Software Based Router and Traffic Generator for Simulation and Testing of IP Network

A Top-Down Modeling Approach for Networks-on-Chip Components Design: A Switch as Case Study

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