Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation

Müller, Hausi A.; Браун,; Gerlach,; Rosenstiel,; Nienhuser,; Zollner,; Bringmann,

doi:10.1109/date.2010.5457147

Cited by 22 publications

(12 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Morphological operations are then applied to clean up small holes in objects, thus avoiding unnecessary processing on objects which are too small to be successfully recognised even if they are traffic signs. Some FPGA-based accelerator solutions exist [10][11][12][13]. The work in [11] uses a MicroBlaze processor on a Virtex-5 with hardware accelerators for colour filtering and morphological operations on images of 320x240 pixels; it computes in 777ms.…”

Section: Flagsand Branchesmentioning

confidence: 99%

“…The work in [11] uses a MicroBlaze processor on a Virtex-5 with hardware accelerators for colour filtering and morphological operations on images of 320x240 pixels; it computes in 777ms. In [12], LEON3 CPUs are used in a Virtex4 FPGA, but this leaves little room for custom accelerators; their design completes within 600ms, but the image size is not discussed. The Altera-based Cyclone II based design in [13] does not consider circular traffic signs.…”

Section: Flagsand Branchesmentioning

confidence: 99%

See 1 more Smart Citation

IPPro: FPGA based image processing processor

Siddiqui

Russell

Bardak

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

View full text Add to dashboard Cite

Abstract-the paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

show abstract

Section: Flagsand Branchesmentioning

confidence: 99%

Section: Flagsand Branchesmentioning

confidence: 99%

IPPro: FPGA based image processing processor

Siddiqui

Russell

Bardak

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

View full text Add to dashboard Cite

show abstract

“…Designing an autonomic computing system with these features could be very challenging [7,13,17]. It is hard to control the interactions between all the autonomic components.…”

Section: Introductionmentioning

confidence: 99%

Formal Specification of Automatic DMARF Based on CSP

Ding

Zhu

2011

2011 Eighth IEEE International Conference and Workshops on Engineering of Autonomic and Autonomous Systems

View full text Add to dashboard Cite

Nowadays, along with computing system becomes more and more complex, it is even harder to control the system effectively. In order to make it easier and ensure the reliability, the computing system needs to be self managed. In 2001, IBM proposed the concept of Autonomic Computing, in which system can manage itself through controlling the interaction of all the consisted parts. However, designing the interaction and verifying the autonomic features are not easy. Formal specification can be very helpful in achieving this. In this paper, we apply Process Algebra CSP in exploring the autonomic features of DMARF system. We give the formal specification of its three features, including selfprotection, self-optimization and self-healing.

show abstract

“…These include conventional (general purpose) computers [20], custom ASIC (application-specific integrated circuit) chips [21], field programmable gate arrays (FPGAs) [22][23][24][25], digital signal processors (DSPs) [26] and also graphic processing units [27]. Although it is difficult to make a direct comparison due to differences in the TSR algorithms employed, the following section discusses the motivation and outcomes of these hardware architectures with respect to the proposed hardware/software solution.…”

Section: Introductionmentioning

confidence: 99%

“…However, the absence of any preprocessing step (sign detection) in the algorithm makes it difficult to recognize a potential sign in a raw image, and the effective accuracy is lower. Another FPGA architecture given in [24] uses a multi-core SoC implementation, targeting a latency of less than 600 ms (maximum latency for a car traveling at a speed of 180 km/h). Specifically, a Gaisler/Pender Electronics FPGA board, GR-CPCI-XC4V [28], is used for hosting a dual core LEON-3 processor and realizing a dedicated hardware accelerator for the support vector machine kernel used in the TSR algorithms.…”

Section: Introductionmentioning

confidence: 99%

Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs

et al. 2015

View full text Add to dashboard Cite

Traffic sign recognition (TSR), taken as an important component of an intelligent vehicle system, has been an emerging research topic in recent years. In this paper, a traffic sign detection system based on color segmentation, speeded-up robust features (SURF) detection and the k-nearest neighbor classifier is introduced. The proposed system benefits from the SURF detection algorithm, which achieves invariance to rotated, skewed and occluded signs. In addition to the accuracy and robustness issues, a TSR system should target a real-time implementation on an embedded system. Therefore, a hardware/software co-design architecture for a Zynq-7000 FPGA is presented as a major objective of this work. The sign detection operations are accelerated by programmable hardware logic that searches the potential candidates for sign classification. Sign recognition and classification uses a feature extraction and matching algorithm, which is implemented as a software component that runs on the embedded ARM CPU.

show abstract

Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation

Cited by 22 publications

References 3 publications

IPPro: FPGA based image processing processor

IPPro: FPGA based image processing processor

Formal Specification of Automatic DMARF Based on CSP

Hardware/Software Co-Design of a Traffic Sign Recognition System Using Zynq FPGAs

Contact Info

Product

Resources

About