1984 International Electron Devices Meeting 1984
DOI: 10.1109/iedm.1984.190753
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Design of an E<sup>2</sup>PROM memory cell less than 100 square microns using 1 micron technology

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“…The memory operation of the aerosol nanocrystal floating-gate MOSFET depends on charge storage in the floating-gate, similar to conventional stacked-gate nonvolatile memory devices. 1 In a silicon nanocrystal nonvolatile memory device, however, charge is not stored on a continuous floating-gate polysilicon layer as is the case in conventional stacked-gate devices, but on a discontinuous floating-gate layer composed of discrete crystalline silicon nanocrystals. [2][3][4] Nanocrystal charge storage offers several potential advantages over conventional stacked-gate nonvolatile memory devices; ͑1͒ a simple low cost floating-gate fabrication process; ͑2͒ improved retention resulting from Coulomb blockade and quantum confinement effects 5 that enable the use of thinner tunnel oxides and lower operating voltages; ͑3͒ reduced punchthrough achieved by eliminating drain-to-floating-gate coupling, allowing higher drain voltages during readout, shorter channel lengths, and smaller cell area; and ͑4͒ excellent immunity to stress induced leakage current and defects within the floating-gate or insulating layers due to the distributed nature of the charge storage in the discontinuous nanocrystal layer.…”
mentioning
confidence: 99%
“…The memory operation of the aerosol nanocrystal floating-gate MOSFET depends on charge storage in the floating-gate, similar to conventional stacked-gate nonvolatile memory devices. 1 In a silicon nanocrystal nonvolatile memory device, however, charge is not stored on a continuous floating-gate polysilicon layer as is the case in conventional stacked-gate devices, but on a discontinuous floating-gate layer composed of discrete crystalline silicon nanocrystals. [2][3][4] Nanocrystal charge storage offers several potential advantages over conventional stacked-gate nonvolatile memory devices; ͑1͒ a simple low cost floating-gate fabrication process; ͑2͒ improved retention resulting from Coulomb blockade and quantum confinement effects 5 that enable the use of thinner tunnel oxides and lower operating voltages; ͑3͒ reduced punchthrough achieved by eliminating drain-to-floating-gate coupling, allowing higher drain voltages during readout, shorter channel lengths, and smaller cell area; and ͑4͒ excellent immunity to stress induced leakage current and defects within the floating-gate or insulating layers due to the distributed nature of the charge storage in the discontinuous nanocrystal layer.…”
mentioning
confidence: 99%