Design of an energy-efficient binarized convolutional neural network accelerator using a nonvolatile field-programmable gate array with only-once-write shifting

Abstract

This paper presents an energy-efficient hardware accelerator for binarized convolutional neural networks (BCNNs). In this BCNN accelerator, a data-shift operation becomes dominant to effectively control input/weight-data streams under limited memory bandwidth. A magnetic-tunnel-junction (MTJ)-based nonvolatile field-programmable gate array (NV-FPGA), where the amount of stored-data updating is minimized in a configurable logic block, is a well-suited hardware platform for implementing such a BCNN accelerator. Owing to the nonvolatile storage capability of the NV-FPGA, not only power consumption in the data-shift operation but also standby power consumption in the idle function block is reduced without losing internal data. It is demonstrated under 45 nm complementary metal–oxide–semiconductor/MTJ process technologies that the energy consumption of the proposed BCNN accelerator is 50.7% lower than that of a BCNN accelerator using a conventional static-random-access-memory-based FPGA.

Design of an active-load-localized single-ended nonvolatile lookup-table circuit for energy-efficient binary-convolutional-neural-network accelerator

“…Figure 11 shows a block diagram of the PE for BCNN operation which is composed of multiply-accumulate (MAC) units, input buffers (IBUFs), and weight buffers (WBUFs). 29) Since the input feature map and the weight are long data stream, the data-shift function performs an important role in the BCNN operation. Thus, the use of the proposed NV-LUT circuit makes it possible to reduce the energy consumption of the data-transferring in the BCNN accelerator.…”

“…Thus, the use of the proposed NV-LUT circuit makes it possible to reduce the energy consumption of the data-transferring in the BCNN accelerator. 29) The number of MAC units is expressed as P R × P C × P M . Therefore, 400 MAC units are used in this case, and thus 7600 6-input LUT circuits are used for implementing 400 MAC units.…”

“…The energy is estimated by the number of LUT circuits used for the BCNN operation. 29) By using the proposed NV-LUT circuit, active energy due to data transfer is reduced since the number of write operations is greatly reduced. Moreover, the standby energy of unused function…”

“…The energy consumption of the BCNN accelerator using the NV-LUT circuit is considerably reduced compared with the SRAM-LUT-based implementation. 29) In such NV-LUT operation, the voltage signal obtained from voltage division between a common active load and a nonvolatile device is an important factor. However, the voltage difference is strongly affected by process variation in the conventional NV-LUT circuit because of its active-load-shared structure.…”