2012
DOI: 10.1109/tvlsi.2011.2109972
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Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications

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Cited by 3 publications
(5 citation statements)
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“…1 consists of two major blocks, i.e. error detection circuit (EDC) and data recovery circuit (DRC), to detect the errors and recover the corresponding data in a specific CUT [9]. The test code generator (TCG) in the architecture utilizes the concepts of RQ code to generate the corresponding test codes for error detection and data recovery.…”
Section: Proposed Edca Designmentioning
confidence: 99%
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“…1 consists of two major blocks, i.e. error detection circuit (EDC) and data recovery circuit (DRC), to detect the errors and recover the corresponding data in a specific CUT [9]. The test code generator (TCG) in the architecture utilizes the concepts of RQ code to generate the corresponding test codes for error detection and data recovery.…”
Section: Proposed Edca Designmentioning
confidence: 99%
“…Fig. 2 shows the proposed EDCA circuit design for a specific PE i of a ME [9]. This architecture consists of blocks that generate the residue and quotient values that are used to detect the errors.…”
Section: Proposed Edca Designmentioning
confidence: 99%
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