Design of an integrated GaN inverter into a multiphase PMSM

Salomez, Florentin; Vienot, Stephane; Zaidi, Bilel; Videt, Arnaud; Duquesne, Thierry; Pichon, Hugot; Semail, Eric; Idir, Nadir

doi:10.1109/vppc49601.2020.9330956

Cited by 8 publications

(7 citation statements)

References 6 publications

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“…In this equivalent circuit, is the open impedance due to capacitive coupling between lines and ground plane, is the impedance of both transmission lines obtained according to the calibration procedure described in Section 2.2 and is the characterized impedance. After transforming the measured S-parameter matrix into admittance parameters , the impedance can be determined using Equation (6). Considering is purely resistive and inductive, the desired inductance value is obtained using Equation (7).…”

Section: S-parameter Measurement Techniquesmentioning

confidence: 99%

“…In this context, Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) are attractive technologies for efficient power conversion at frequencies higher than the megahertz due to their higher electron mobility and lower interelectrode capacitances than silicon components [1]. Several recent works have brought to light the great potential of GaN power devices for high power density converter design [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

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Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

et al. 2021

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Due to the high switching speed of Gallium Nitride (GaN) transistors, parasitic inductances have significant impacts on power losses and electromagnetic interferences (EMI) in GaN-based power converters. Thus, the proper design of high-frequency converters in a simulation tool requires accurate electromagnetic (EM) modeling of the commutation loops. This work proposes an EM modeling of the parasitic inductance of a GaN-based commutation cell on a printed circuit board (PCB) using Advanced Design System (ADS®) software. Two different PCB designs of the commutation loop, lateral (single-sided) and vertical (double-sided) are characterized in terms of parasitic inductance contribution. An experimental approach based on S-parameters, the Cold FET technique and a specific calibration procedure is developed to obtain reference values for comparison with the proposed models. First, lateral and vertical PCB loop inductances are extracted. Then, the whole commutation loop inductances including the packaging of the GaN transistors are determined by developing an EM model of the device’s internal parasitic. The switching waveforms of the GaN transistors in a 1 MHz DC/DC converter are given for the different commutation loop designs. Finally, a discussion is proposed on the presented results and the development of advanced tools for high-frequency GaN-based power electronics design.

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Section: S-parameter Measurement Techniquesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

et al. 2021

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“…A similar dead time evaluation for the Q 2 turn-on (t dt,on ) switching event may be considered. During dead time, equivalent body diode free-wheeling acts to introduce further power losses as described in (15) where the voltage drop V F depends on the GaN FET technology characteristics.…”

Section: Dead Time Effect On the Motor Drives Invertersmentioning

confidence: 99%

“…If t dt,on is equal to t dt,off the dead time is simply defined as t dt . From the modelling of dead time starting from (15), it is possible to evaluate losses related to the variation of dead time at different output currents as shown in Figure 14a. As shown in Figure 14a, dead-time losses due to the body diode voltage drop V F increase linearly with total dead-time widening.…”

Section: Dead Time Effect On the Motor Drives Invertersmentioning

confidence: 99%

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Low-Voltage GaN FETs in Motor Control Application; Issues and Advantages: A Review

et al. 2021

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The efficiency and power density improvement of power switching converters play a crucial role in energy conversion. In the field of motor control, this requires an increase in the converter switching frequency together with a reduction in the switching legs’ dead time. This target turns out to be complex when using pure silicon switch technologies. Gallium Nitride (GaN) devices have appeared in the switching device arena in recent years and feature much more favorable static and dynamic characteristics compared to pure silicon devices. In the field of motion control, there is a growing use of GaN devices, especially in low voltage applications. This paper provides guidelines for designers on the optimal use of GaN FETs in motor control applications, identifying the advantages and discussing the main issues. In this work, primarily an experimental evaluation of GaN FETs in a low voltage electrical drive is carried out. The experimental investigation is obtained through two different experimental boards to highlight the switching legs’ behavior in several operative conditions and different implementations. In this evaluative approach, the main GaN FETs’ technological aspects and issues are recalled and consequently linked to motion control requirements. The device’s fast switching transients combined with reduced direct resistance contribute to decreased power losses. Thus, in GaN FETs, a high switching frequency with a strong decrease in dead time is achievable. The reduced dead time impact on power loss management and improvement of output waveforms quality is analyzed and discussed in this paper. Furthermore, input filter capacitor design matters correlated with increasing switching frequency are pointed out. Finally, the voltage transients slope effect (dv/dt) is considered and correlated with low voltage motor drives requirements.

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Conceptual design of a distributed electric anti-torque system for enhanced helicopter safety and performance

Brunetti,

Nesci,

Bianchi

2023

CEAS Aeronaut J

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Design of an integrated GaN inverter into a multiphase PMSM

Cited by 8 publications

References 6 publications

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Parasitic Loop Inductances Reduction in the PCB Layout in GaN-Based Power Converters Using S-Parameters and EM Simulations

Low-Voltage GaN FETs in Motor Control Application; Issues and Advantages: A Review

Conceptual design of a distributed electric anti-torque system for enhanced helicopter safety and performance

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