APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems 2006
DOI: 10.1109/apccas.2006.342428
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Design of AND and NAND Logic Gate Using NDR-BASED Circuit Suitable for CMOS Process

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Cited by 4 publications
(6 citation statements)
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“…To characterize this effect, the most important parameter is the peak-to-valley ratio (PVR), which is defined by I(V Peak )/I(V Valley ). 17 A large and stable PVR is highly relevant for logic applications. 15,17 As the electron concentration in the Ge channel can be modulated by varying V CG, a tunable PVR is observed.…”
Section: Resultsmentioning
confidence: 99%
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“…To characterize this effect, the most important parameter is the peak-to-valley ratio (PVR), which is defined by I(V Peak )/I(V Valley ). 17 A large and stable PVR is highly relevant for logic applications. 15,17 As the electron concentration in the Ge channel can be modulated by varying V CG, a tunable PVR is observed.…”
Section: Resultsmentioning
confidence: 99%
“…17 A large and stable PVR is highly relevant for logic applications. 15,17 As the electron concentration in the Ge channel can be modulated by varying V CG, a tunable PVR is observed. Consequently, starting with V CG = 3 V the PVR increases from 1.2 to 7.7 at V CG = 5 V.…”
Section: Resultsmentioning
confidence: 99%
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