Design of area-efficient modified decoder-based imprecise multiplier for error-resilient applications

Anguraj, Parthibaraj; Krishnan, Thiruvenkadam

doi:10.1016/j.mejo.2023.105957

Cited by 1 publication

(2 citation statements)

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“…in partial product values p 7 -p 0 (10110111) 2 ; A 3 -A 0 (1111) 2 is multiplied by B 7 -B 4 (1111) 2 , yielding partial product values p 15 -p 8 (11100001) 2 ; A 7 -A 4 (1111) 2 is multiplied by B 3 -B 0 (1111) 2 , producing partial product values p 23p 16 (10110111) 2 ; A 7 -A 4 (1111) 2 is multiplied by B 7 -B 4 (1111) 2 , generating partial product values p 31 -p 24 (11100001) 2 . The 3-bit decoder scheme's operation is detailed in [15]. To provide clearer insights, we present a numerical demonstration of a 4×4 module employing the 3-bit decoder in conjunction with AND logic, depicted in Fig.…”

Section: Proposed Inexact Multiplier Structuresmentioning

confidence: 99%

“…Nonetheless, despite outperforming previous imprecise models, the 2-bit decoder logic-based imprecise multiplier still contends with high design complexity. To address this further, [15] proposes a 3-bit decoder logic-based imprecise multiplier. Here, the 8-bit multiplier bits (A) are grouped via 3bit decoder logic on the LSB side (A 6 -A 0 ), with exact AND logic utilized on the MSB side (A 8 -A 7 ) for partial product generation.…”

Section: Introductionmentioning

confidence: 99%

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Developing and Assessinginexact Multiplierarchitectures for Imageprocessing

Anguraj,

Krishnan

2024

Preprint

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In the realm of approximate computing, the inexact multiplier architecture stands out as a cornerstone, playing a pivotal role acrosserror-tolerated applications. This article delves into the intricacies ofthree distinct inexact multiplier architectures tailored specifically forimage processing tasks. The study revolves around efficiently partitioning the partial product stage into smaller modules and thenemploying decoder algorithms/truncation techniques, to obtain thesuggested multiplier’s final result. The resulting 8×8 imprecise multipliers are engineered with reduced design overhead and reasonableerror metrics. Through simulation with the Cadence RTL compilerusing TSMC 90 nm technology, the realization showcases substantialarea and power savings compared to conventional imprecise multipliers. Comparing one of the proposed approximate models to precisemultipliers reveals significant reductions in both the area and thepower requirement, amounting to 37.19% and 46.14%, respectively, allwhile ensuring acceptable error metrics. Furthermore, in comparison toalternative approximation multiplier designs, the suggested 8×8 multiplier showcases superior performance metrics. It achieves justifiablemean Structural Similarity Index (SSI) values, making it particularlyadvantageous for tasks such as picture multiplication and sharpening.

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Section: Proposed Inexact Multiplier Structuresmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%