Design of asynchronous systems on FPGA using direct mapping and synchronous specification

Abstract

Complex synchronous digital systems can be implemented on FPGAs (Field Programmable Gate Arrays), but due to the global clock, might have problems with clock skew, performance degradation and increased of power consumed. An alternative to these designs is the asynchronous paradigm that solves the problems related to the clock. However it is difficult to design asynchronous circuits, especially in the FPGA platform. This work presents in the style of asynchronous FSM (finite state machine) + data-path a method that implements asynchronous digital systems on FPGAs. The proposed method uses the tools of paradigm synchronous, thus synthesizes without the knowledge of asynchronous logic. Our method synthesizes the asynchronous FSM by direct mapping from the conventional state transition graph. Through a case study, it is shown the simplicity of the proposed methodology.

EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline

“…As a typical example of the former, there are design methods in which the specifications of a circuit are defined by using a so-called signal transition graph (STG), which is a directed graph for expressing the order of signal transitions. The defined specification is mechanically synthesized into simplified logic gates with wires [7], [8]. Support tools for specification definitions and synthesis have been proposed [9].…”