Design of CMOS low-dropout voltage regulator for power management integrated circuit in 0.18-µm technology

Murad, S. A. Z.; Harun, A.; Isa, Mohd Nazrin Md; Mohyar, S. N.; Sapawi, Rohana; Karim, Jamilah

doi:10.1063/1.5142098

Cited by 4 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A basic LDO voltage regulator topology usually consists of an error amplifier, a voltage reference, a pass device, an external load capacitor with small amount of internal resistance and a resistive feedback network [6]. Figure 1 shows the overall topology of LDO voltage regulator.…”

Section: Basic Ldo Voltage Regulatormentioning

confidence: 99%

“…The error signal will control the gate of the pass transistor for maintaining constant output voltage to supply a variable current to the load circuit. The OTA is suitable for error amplifier since the output of error amplifier is utilized to drive the gate of the pass transistor [6]. Therefore, in the proposed design the OTA is implemented as an error amplifier.…”

Section: Basic Ldo Voltage Regulatormentioning

confidence: 99%

“…These mobile gadgets advertise requires low voltage and low quiescent current flow to increase the battery efficiency and longevity. The requirement for low voltage is intrinsic to portable low power gadgets and validated by lower breakdown voltages resulting from reduction in feature size [6]. Low quiescent current in a batteryoperated system is an intrinsic performance parameter because it partially determines battery life.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Very Low-Dropout Voltage Regulator in 0.18-M Cmos Technology for Power Management System

et al. 2020

View full text Add to dashboard Cite

This paper proposes the design of a very low-dropout (LDO) voltage regulator in 0.18-mm CMOS technology. The proposed LDO regulator consists of voltage reference, symmetrical operational transconductance amplifier (OTA), PMOS transistor, resistive feedback network and output capacitor. The NMOS symmetrical OTA is implemented as an error amplifier and a PMOS transistor is employed as a pass device to improve gain and minimize low dropout voltage, respectively. The proposed design is simulated using Spectre simulator in Cadence software to verify its regulator performance. The simulation results show that the proposed LDO is capable to operate from a supply voltage of 1.7-2.0 V with a low dropout voltage of 19.3 mV at a maximum 50 mA load current to regulate output voltage 1.5 V. The active chip is 2.96 mm2 in size. The performance of the proposed LDO is suitable to enhance power management for system on chip (SoC) applications.

show abstract

Section: Basic Ldo Voltage Regulatormentioning

confidence: 99%

Section: Basic Ldo Voltage Regulatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation