Design of CNFET based power- and variability-aware nonvolatile RRAM cell

Pal, Soumitra; Gupta, Vivek; Islam, Aminul

doi:10.1016/j.mejo.2019.02.009

Cited by 9 publications

(2 citation statements)

References 26 publications

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“…The read delay or read access time (

T_{RA}

) for differential reading cells isestimated as mentioned in [10, 28–30]. On the other hand, for single‐ended reading cells like SEDF9T,read delay is estimated according to [12].…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Selfrefreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/ write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

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“…The read delay or read access time (

T_{RA}

) for differential reading cells isestimated as mentioned in [10, 28–30]. On the other hand, for single‐ended reading cells like SEDF9T,read delay is estimated according to [12].…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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“…T RA (read access time or read delay) is estimated from the time the wordline crosses 50% of its full swing to the time that one of the bitlines (BL/BLB) is discharged by 50 mV from its initial high level. 3,6,21,22 The value of the bitline capacitance and the amount of read current through the access transistor are the major factors which impact the T RA . All the 10T comparison cells and RHD12T have only one identically sized NMOS access transistor connected to each bitline.…”

Section: Read Delay Comparisonmentioning

confidence: 99%

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

Pal

Divya

et al. 2021

Circuit Theory & Apps

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In advanced technology, static random-access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high-energy particle strikes, which cause soft-error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation-hardened readdecoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read-decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02Â/1.06Â/1.07Â/1.08Â over NS10T/RHD12T/PS10T/RHBD10T at V DD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single-event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. K E Y W O R D Sdigital circuit, low power design, memory design, read stability, SRAM | INTRODUCTIONSatellites have become an integral part of human society, as we rely on satellite communication for a wide range of services, from meteorology to disaster monitoring, from navigation systems to military operations, and so on. 1 As the technology is advancing, lightweight satellites are replacing heavyweight satellites because of their higher manufacturing cost. 2 Since lightweight satellites have limited resources, they require high-density memory cells, and static random-access memory (SRAM) cells are the best alternative for space applications because of their high packing density and improved logic performance. 1 Space presents extreme conditions, like temperature fluctuations and radiation. Due to the weak geomagnetic field in space, radiation and energized particles increase. To withstand this harsh environment, special electronic components and circuits are used. Once a radiation particle strikes a logic circuit at its sensitive node, it generates electron-hole pairs (Figure 1A). These pairs become separated and accumulate at the sensitive node. 3 The accumulated charge at the sensitive node then generates a transient voltage pulse. If enough charge (i.e., critical charge, Q C ) is

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