Design of compactors for signature-analyzers in built-in self-test

Wohl, P.; Waicukauski, J.A.; Williams, T.W.

doi:10.1109/test.2001.966618

Cited by 69 publications

(28 citation statements)

References 8 publications

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“…So this style of spread network is called as "compacting spread network". The compression bound and synthesis are described in [1,12]. The design theorems of [1] cannot be directly used to our compactor since they do not consider the error cancellations in different cycles.…”

Section: Design Techniques Of Response Spread Networkmentioning

confidence: 99%

“…[11] presents an OPMISR technique which can double the number of scan chains using an on-product MISR. [12] presents a design technique of space compactor and MISR which can avoid the twoerror cancellation. However, the above two techniques do not have an effective way to eliminate the X bits in the scan chain whose outputs are not known during simulation.…”

Section: Introductionmentioning

confidence: 99%

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Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Han

et al. 2005

J Comput Sci Technol

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This paper presents a test resource partitioning technique based on an efficient response compaction design called quotient compactor(q-Compactor). Because q-Compactor is a single-output compactor, high compaction ratios can be obtained even for chips with a small number of outputs. Some theorems for the design of q-Compactor are presented to achieve full diagnostic ability, minimize error cancellation and handle unknown bits in the outputs of the circuit under test (CUT). The q-Compactor can also be moved to the load-board, so as to compact the output response of the CUT even during functional testing. Therefore, the number of tester channels required to test the chip is significantly reduced. The experimental results on the ISCAS '89 benchmark circuits and an MPEG 2 decoder SoC show that the proposed compaction scheme is very efficient.

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Section: Design Techniques Of Response Spread Networkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Han

et al. 2005

J Comput Sci Technol

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show abstract

“…A costly alternative would be inserting test points to mask x's right at their sources at the expense of area cost and performance degradation. Combinational compaction solutions, mostly XOR-based, are also utilized for response compaction [13,14,15,16,17,18,19]. Some of these techniques build the response compactor based on fault sensitization information under a particular fault model assumption [13,14,15,16,17], while response unknown bit and unmodeled defect coverage issues are overlooked.…”

Section: Introductionmentioning

confidence: 99%

Toggle-Based Masking Scheme for Clustered Unknown Response Bits

Sinanoglu

2011

2011 Sixteenth IEEE European Test Symposium

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Masking schemes typically suffer from over-masking of bits that may possess fault effect information, degrading test quality levels. Unknown response bits (x's) exhibit a clustered distribution in responses due to structural proximity of x sources. In this work, we propose a toggle-based masking scheme that is capable of delivering very high observability levels in the case of clustered x distributions. The proposed scheme assigns a single-bit state to each chain, dictating whether the chain will be masked or observed. Clustered distribution of x's enables an infrequent switching of state information, minimizing the amount of mask data that selectively toggles the state of chains. Thus, only a few mask channels are needed to control the proposed masking hardware, enabling the blocking of all x's while over-masking a small number of non-x bits. Capability to mask all x's enables the use of a MISR in conjunction, and thus eliminates the need for any scan-out channels, translating into enhanced parallelism in multi-site testing. Results on industrial test cases show that the proposed masking scheme is capable of minimizing or even eliminating over-masking, delivering near-optimal test quality levels.

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“…Masking signals are transferred through tester channels and they are used to specify which scan chain outputs should be masked during which clock cycles. Many schemes for X-masking hardware design and mask control data compression have been developed [1]- [3], [11]- [14], [17], [19], [23]- [26]. In many cases, the resolution of the masking is reduced in order to keep the amount of mask data at reasonable levels (e.g., an entire scan chain or an entire scan slice may be masked).…”

mentioning

confidence: 99%

$X$-Canceling MISR Architectures for Output Response Compaction With Unknown Values

Yang

Touba

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, an X-tolerant multiple-input signature register (MISR) compaction methodology that compacts output responses containing unknown X values is described. Each bit of the MISR signature is expressed as a linear combination in terms of Xs by symbolic simulation. Linearly dependent combinations of the signature bits are identified with Gaussian elimination and XORed to remove X values and yield deterministic values. Two X-canceling MISR architectures are proposed and analyzed with industrial designs. This paper also shows the correlation between the estimated result based on idealized modeling and the actual data for real circuits for error coverage, hardware overhead, and other metrics. Experimental results indicate that high error coverage can be achieved with X-canceling MISR configurations and it highly correlates with actual results.

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Design of compactors for signature-analyzers in built-in self-test

Cited by 69 publications

References 8 publications

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction

Toggle-Based Masking Scheme for Clustered Unknown Response Bits

$X$-Canceling MISR Architectures for Output Response Compaction With Unknown Values

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