Design of DADDA Multiplier Using High Performance and Low Power Full Adder

S.Nagaleela,; G.Shanthi,; Manisha, Boppa; Bharath, Palle; Praneeth, Erram

doi:10.1109/icccnt56998.2023.10308152

2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT) 2023

DOI: 10.1109/icccnt56998.2023.10308152

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Design of DADDA Multiplier Using High Performance and Low Power Full Adder

S.Nagaleela,

G.Shanthi,

Boppa Manisha

et al.

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2024

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Cited by 4 publications

References 21 publications

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2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)

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VLSI Design of High Performance FIR Filter using High Speed Hybrid Multiplier

Nagaleela,

Swetha,

Chandrika

et al. 2024

2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)

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Design of Shift Registers Using DG-FinFET for Low Power Applications

Shanthi,

Naga Vaishnavi,

Manasa

et al. 2024

2024 7th International Conference on Devices, Circuits and Systems (ICDCS)

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Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology

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Ashwini

et al. 2024

2024 5th International Conference for Emerging Technology (INCET)

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Design of DADDA Multiplier Using High Performance and Low Power Full Adder

Cited by 4 publications

References 21 publications

VLSI Design of High Performance FIR Filter using High Speed Hybrid Multiplier

VLSI Design of High Performance FIR Filter using High Speed Hybrid Multiplier

Design of Shift Registers Using DG-FinFET for Low Power Applications

Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology

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