Design of delay efficient modified 16 bit Wallace multiplier

Ram, G. Challa; Rani, D. Sudha; Balasaikesava, R.; Sindhuri, K. Bala

doi:10.1109/rteict.2016.7808163

Cited by 22 publications

(10 citation statements)

References 2 publications

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“…To demonstrate the fact that the improved results are due to the proposed architecture instead of the tools and technology, the design has been compared to the relevant literature which utilized the same technology and tools as used in this work. The proposed design was compared with [7] and [4], and the comparison results are tabulated in Table 4. The proposed design requires approximately 70% fewer resources (including flip-flops, LUTs and slice registers) as compared with [7] and [4] to produce the same multiplication.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…The former is a high-speed algorithm as the partial products are generated and added concurrently [5] while the latter one is more efficient in terms of hardware utilization [6]. An array multiplier is the simplest architecture but its drawback is its higher number of partial products as compared to the tree multipliers and hence it consumes more resources and time [7]. Wallace tree is also an advanced, pipelined, fast and highly used algorithm [8].…”

Section: Introductionmentioning

confidence: 99%

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An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

et al. 2019

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A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-andconquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

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Section: Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

et al. 2019

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“…Now a day's, the electronic technological developments of the present world are changing rapidly in construction of small size, less power and lower delay devices. The processing speed of the device is improved due to limiting the power dissipation [3]. A survey had been carried out with different multiplier algorithms for MAC architecture design [7][8].…”

Section: Introductionmentioning

confidence: 99%

“…Tree based multipliers like Binary tree and Wallace tree, array based multipliers such as Braun, Booth and Baugh Woolley are some of the parallel multipliers [2] [9]. It is shown that the parallel multipliers are faster than the traditional multipliers, Wallace and Dadda multipliers come under parallel multipliers [3]. In general, for n x n bit multiplication process an array of n-AND gates required to generate partial products in partial production generation stage, an array of n 2 adders (adder may be full adder or half adder) to sum the n 2 partial product terms for partial product accumulation stage and addition stage.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

Kumar¹,

Sudhakar²,

Suman³

2019

IJITEE

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Arithmetic operations play a major role in digital circuit design like adders, multipliers etc. Multiplication is an important fundamental arithmetic operation in high performance systems such as microprocessor and digital signal processors circuits. Implementation of multipliers using compressor circuit over conventional adders will reduce the number of levels of addition, which will in turn reduces the latency of the multiplier. Multiplier module is most likely the essential part of MAC (Multiplier-Accumulator) unit design. Compressor based multipliers in MAC architecture design results high performance. FPGA and ASIC implementations of 4:2 compressor based 32-bit Wallace and Dadda multipliers can be done by using Xilinx Vivado and Cadence CMOS technology tools. These results are compared with other multiplier designs with respect to area, latency and power dissipation.

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“…Various strategies have been devoted to decreasing the power of different type of multipliers [1,2,3,4,5,6,7,8,9,10]. Some of them are briefly introduced below.…”

Section: Introductionmentioning

confidence: 99%

Design of low-power low-area asynchronous iterative multiplier

You

Hei

Jia

et al. 2019

IEICE Electron. Express

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In this paper, a 16 times 16 low-power low-area asynchronous iterative multiplier is proposed. The multiplier diminishes 2 bits at a time with an iterative structure, to filter out the useless switching activities, we employ a finishing detector to dynamically detect the end of the computation and stop iteration ahead of schedule. Additionally, with the employment of finishing detectors, the proposed multiplier could provide a much faster average speed than synchronous approach. Post-layout simulation results show that the asynchronous multiplier offers up to 74% power reduction compared with the synchronous design. Simultaneously, the proposed design also exhibits a prominent area reduction compared with other non-iterative multiplier benefited from the iterative architecture.

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Design of delay efficient modified 16 bit Wallace multiplier

Cited by 22 publications

References 2 publications

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

Design and Implementation of Compressor based 32-bit Multipliers for MAC Architecture

Design of low-power low-area asynchronous iterative multiplier

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